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high performance, polyphase energy metering afe data she et ade9078 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. howeve r, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or othe rwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2016 analog devices, inc. all rights reserved. technical support www.analog.com features 7 high p erformance analog - to - digital converters ( adcs ) 101 db signal - to - noise ratio ( snr ) 10, 000:1 d ynamic r ange wide i nput r ange: 1 v, 0.707 v rms full scale differential i nputs 25 ppm/ c m ax imum c hannel t emperature d rift (including adc, i nternal v ref , and pga drift) enabling class 0.2 meters with standard external components power q uality m easure ments line f requency : 1 measurement per phase zero c rossing detection , z ero - c rossing t imeout phase a ngle measurem ents supports c urrent t ransformers (cts) and rogowski coil (di/dt) sensors mu l tiple range phase/gain compensation for cts digital i ntegrator for rogowski coils flexible w aveform b uffer able to resample waveform to ensure 64 points per line cycle for ease of external harmonic analysis events can trigger waveform storage simplifies data collection for iec 6 1000- 4 - 7 harmonic analysis advanced m etrology f eature s et total active power , volt - amperes reactive ( va r ) , volt - amperes ( va ) , w atth ou r, var - h ou r , and va - h ou r fundamental var and var - h ou r current and voltage rms per phase (xirms, xvrms) supports a ctive e nergy s tandards: iec 62053 - 21, iec 62053 - 22; en50470 - 3; oiml r46, ansi c12.20 supports r eactive e nergy s tandards: iec 6205 3 - 23, iec 62053 - 4 high speed communication port 10 mhz serial peripheral interface (spi ) applications p olyphase meters power quality monitoring protective device general description the ade9078 1 is a highly accurate, fully integrated energy metering device. interfacing with both current transformer (ct) and rogowski coil sensors, the ade9078 enables users to develop a 3 - phase metrology platform, which achieves high performance fo r class 1 up to cl ass 0.2 meters. functional block dia gram sinc4 and decim a tion ldo 1.25v reference cf1 to cf4 irq0 irq1 spi ade9078 pga adc pga adc pga adc pga adc pga adc pga adc pga adc metrology features (per phase) irms, vrms active power, va watthour, va-hr waveform buffer line frequency etc. 14331-001 figure 1. the ade9078 integrates seven high performances adcs and a flexibl e dsp core. an integrated high end reference ensures low drift over temperature with a combined drift of less than 25 ppm/c max imum per channel , each of which include s a p rogrammable gain amplifier ( p ga ) and adc. the ade9078 offers an integrated flexible waveform buffer that stores samples at a fixed data rate or a sampling rate that varies b ased on line frequency to ensure 64 points per line cycle. these t wo options make it easy to implement harmonic analysis in an external processor a ccording to iec 61000 - 4 - 7. two power modes are provided to enable detection of meter tampering: psm2 uses a low power comparator to compare cur rent channels to a threshold and indicates whether it i s exceeded on the irq0 and irq1 outputs ; psm1 enables fast measurem ent of current and voltage rms ( xvrms and xirms ) , active power , an d va r during a tamper. the ade9078 allows advanced and highly accurate energy measurements, enabling one platform to cover a wide range of meters, through a combination of various high end metrology features and superior analog performance. 1 protected by u.s. patents 5,952,849; 6,873,065; 7,075,329; 6,262,600; 7,489,526; 7,558,080. other patents are pending.
ade9078* product page quick links last content update: 11/01/2016 comparable parts view a parametric search of comparable parts evaluation kits ? ade9078 evaluation board documentation application notes ? an-1415: ade9078 low power mode for no voltage detection data sheet ? ade9078: high performance, polyphase energy metering afe data sheet user guides ? ug-953: evaluating the ade9078 high performance, polyphase energy metering analog front end (afe) tools and simulations ? ade9078 calibration tool design resources ? ade9078 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ade9078 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
ade9078 data sheet rev. 0 | page 2 of 107 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 3 ? specifications ..................................................................................... 4 ? timing characteristics ................................................................ 7 ? absolute maximum ratings ............................................................ 9 ? thermal resistance ...................................................................... 9 ? esd caution .................................................................................. 9 ? pin configuration and function descriptions ........................... 10 ? typical performance characteristics ........................................... 12 ? total energy linearity over supply and temperature ........... 12 ? fundamental energy linearity with fifth harmonic over supply and temperature ............................................................ 13 ? total energy error over frequency .......................................... 14 ? rms linearity over temperature and rms error over frequency .................................................................................... 15 ? energy linearity repeatability ................................................. 16 ? total energy and rms linearity with integrator on ............ 17 ? total energy error over frequency with integrator on ....... 18 ? test circuit ...................................................................................... 19 ? terminology .................................................................................... 20 ? theory of operation ..................................................................... 22 ? adc ............................................................................................. 22 ? crystal oscillator/external clock ............................................ 24 ? power management .................................................................... 25 ? measurements (normal mode) ................................................ 27 ? measurements (psm1) .............................................................. 45 ? measurements (psm2) .............................................................. 54 ? key features .................................................................................... 55 ? flexible waveform buffer with resampling ........................... 55 ? multipoint phase/gain calibration ......................................... 55 ? rms of sum of instantaneous currents measurement ......... 55 ? tamper modes ............................................................................ 55 ? power factor................................................................................ 55 ? zero-crossing timeout detection ........................................... 55 ? line period measurement ......................................................... 55 ? angle measurement ................................................................... 55 ? phase sequence error detection .............................................. 55 ? quick start ....................................................................................... 56 ? applications information .............................................................. 57 ? non-blondel compliant meters ............................................... 58 ? applying the ade9078 to a 4-wire wye service ...................... 58 ? applying the ade9078 to a 3-wire delta service ................. 59 ? applying the ade9078 to a non-blondel compliant, 4-wire wye service ................................................................................. 60 ? applying the ade9078 to a non-blondel compliant, 4-wire delta service ............................................................................... 60 ? service type summary .............................................................. 60 ? accessing on-chip data ............................................................... 62 ? spi protocol overview .............................................................. 62 ? spi write ...................................................................................... 63 ? spi read ....................................................................................... 63 ? spi burst read ............................................................................ 63 ? spi protocol crc ....................................................................... 64 ? additional communication verification registers ............... 64 ? crc of configuration registers............................................... 65 ? configuration lock .................................................................... 65 ? waveform buffer ............................................................................ 66 ? fixed data rate waveforms ...................................................... 67 ? fixed data rate waveforms filling and trigger-based modes .. 68 ? resampled waveforms .............................................................. 70 ? configuring the waveform buffer ........................................... 70 ? burst read waveform buffer samples from spi .................... 71 ? interrupts/events ............................................................................ 74 ? interrupts ( irq0 and irq1 ) ..................................................... 74 ? event ........................................................................................ 74 ? status bits in additional registers ........................................... 74 ? troubleshooting .............................................................................. 75 ? spi does not work .................................................................... 75 ? psm2_cfg register value is not retained when going from psm2 or psm3 to psm0 .................................................. 75 ? register information ...................................................................... 76 ? register details ........................................................................... 88 ? outline dimensions ..................................................................... 107 ? ordering guide ........................................................................ 107 ?
data sheet ade9078 rev. 0 | page 3 of 107 revision history 8/2016revision 0: initial version
ade9078 data sheet rev. 0 | page 4 of 107 specifications v dd = 2 .7 v to 3.63 v, gnd = agnd = dgnd = 0 v, on - chip reference, clkin = 12.288 mhz crystal ( xtal ) , t min to t max = ?40c to +85c for min imum and maximum specifications , t a = 25c (typical) for typical specifications . table 1 . 1 parameter min typ max unit test conditions/comments accuracy measurement error per phase total active energy 0.1 % over a dynamic range of 5000 to 1, 10 sec accumulation ; g ain compensation only 0. 2 % over a dynamic range of 10 , 000 to 1, 2 0 sec accumulation ; gain compensation only total reactive energy 0.1 % over a dynamic range of 5000 to 1, 10 sec accumulation ; gain compensation only 0.2 % over a dynamic range of 10 , 000 to 1, 20 sec accumulation ; gain compensation only total apparent energy 0.1 % over a dynamic range of 1000 to 1, 2 sec accumulation 0.5 % over a dynamic range of 5000 to 1, 10 sec accumulation fundamental reactive 0.1 % over a dynamic range of 5000 to 1, 2 sec accumulation 0.2 % over a dynamic range of 10 , 000 to 1, 2 0 sec accumulation irms , v rms 0.1 % over a dynamic range of 1000 to 1 0.5 % over a dynamic range of 5000 to 1 active power , var 0.2 % over a dynamic range of 5000 to 1, 1 sec accumulation power factor (pf) 0.001 over a dynamic range of 5000 to 1 64 - p oint per l ine c ycle r esampled d ata 0.1 % a n fft is performed to receive the magni - tude response ; t his error is the worst case error in the f undamental magnitude caused by resampling algorithm distortion ; i nput signal is 50 hz fundamental on voltage channel and fundamental with ninth har - monic at half of full scale on current channel 0.3 % a n fft is performed to receive the magni - tude response; this error is the m agnitude error of ninth harmonic caused by the resampling algorithm distortion input signal is 50 hz fundamental with ninth harmonic at half of full scale on current channel ? 72 db amplitude of highest spur ; i nput signal is 50 hz fundamental and ninth harmonic at half of full scale on the current channel 3 % a n fft is performed to receive the magni - tude response ; t his error is the magnitude error of 31 st harmonic caused by resampling algorithm distortion ; i nput signal is 50 hz fundamental with 31 st harm onic at half of full scale on the current channel ? 38 db amplitude of highest spur ; i nput signal is 50 hz fundamental and 31 st harm onic at half of full scale on the current channel line period measurement 0.001 hz resolution at 50 hz current to current, voltage to voltage , and voltage to current angle measurement 0.036 degrees resolution at 50 hz ; v oltage and c urrent at 1/10 th of full scale psm1 irms 0.2 % accuracy achieved 40 ms after entering psm1 mode at 600:1
data sheet ade9078 rev. 0 | page 5 of 107 parameter min typ max unit test conditions/comments psm1 active power 0.2 % accuracy achieved 40 ms after entering psm1 mode at 600:1 psm2 peak current detection 5 % accuracy of current detection threshold, achieved 120 ms after entering psm2 mode at 660:1 adc see the adc section pga gain settings (gain) 1, 2, or 4 v/v pga gain setting is referred to as gain differential input voltage range (vxp ? vxn, ixp ? ixn) ?1/gain +1/gain v 0.707 v rms; when v ref = 1.25 v, this voltage corresponds to 53 million codes maximum operating voltage on analog input pins (vxp, vxn, ixp, and ixn) ?0.6 0.6 v voltage on the pin with respect to ground (gnd = agnd = dgnd = refgnd), v ref = 1.25 v signal-to-noise ratio (snr) 2 v in = full scale/gain; see the terminology section pga = 1 101 db 4 ksps sinc4 + infinite impulse response (iir) low-pass filter (lpf) output 97 db 16 ksps sinc4 output pga = 4 97 db 4 ksps sinc4 + iir lpf output 94 db 16 ksps sinc4 output total harmonic distortion (thd) 2 see the terminology section pga = 1 ?106 db 4 ksps sinc4 + iir lpf output ?106 db 16 ksps sinc4 output pga = 4 ?115 db 4 ksps sinc4 + iir lpf output ?112 db 16 ksps sinc4 output signal-to-noise and distortion ratio (sinad) 2 see the terminology section pga = 1 100 db 4 ksps sinc4 + iir lpf output 96 db 16 ksps sinc4 output pga = 4 96 db 4 ksps sinc4 + iir lpf output 93 db 16 ksps sinc4 output spurious-free dynamic range (sfdr) 2 see the terminology section pga = 1 110 db 4 ksps sinc4 + iir lpf output output pass band (?0.1 db) see the terminology section sinc4 outputs 0.672 khz 16 ksps sinc4 output sinc4 + iir lpf outputs 0.672 khz 4 ksps output output bandwidth (?3 db) 2 see the terminology section sinc4 outputs 3.6325 khz 16 ksps sinc4 output sinc4 + iir lpf outputs 1.6 khz 4 ksps output crosstalk 2 ?120 db see the terminology section, at 50 hz and 60 hz ac power supply rejection ratio (ac psrr) 2 ?120 db see the terminology section, at 50 hz and 60 hz ac common-mode rejection ratio (ac cmrr) 2 ?115 db at 100 hz and 120 hz gain error 0.3 1 % see the terminology section gain drift 2 3 ppm/c see the terminology section offset 0.36 3.8 mv see the terminology section offset drift 2 0 6 v/c see the terminology section
ade9078 data sheet rev. 0 | page 6 of 107 parameter min typ max unit test conditions/comments channel drift (pga, adc, internal voltage reference) 7 25 ppm/c pga = 1, internal v ref 7 25 ppm/c pga = 2, internal v ref 7 25 ppm/c pga = 4, internal v ref differential input impedance (dc) 330 366 k see the terminology section, pga = 1 160 180 k pga = 2 80 90 k pga = 4 internal voltage reference nominal 1.25 v 1 mv voltage reference 1.250 v t a = 25c, ref pin temperature coefficient 2 5 20 ppm/c t a = ?40c to +85c external voltage reference ? external voltage reference input voltage (ref) 1.2, 1.25 v refgnd must be tied to gnd, agnd, and dgnd; 1.25 v external reference is preferred; the full-scale values mentioned in this data sheet are for a voltage reference of 1.25 v average reference current 120 a/v crystal oscillator clkin = 12.288 mhz 30 ppm (see the crystal oscillator/external clock section) input clock frequency 12.165 12.288 12.411 mhz internal capacitance on clkin and clkout 4 pf internal feedback resistance between clkin and clkout ? 2.5 m transconductance (g m ) 9 ma/v external clock input input clock frequency 12.165 12.288 12.411 mhz duty cycle 2 45:55 50:50 55:45 % clkin logic inputs 3.3 v tolerant input voltage high, v inh 1.2 v v dd = 2.7 v to 3.63 v low, v inl 0.5 v v dd = 2.7 v to 3.63 v logic inputs pm0, pm1, reset , mosi, sclk, and ss input voltage high, v inh ? 2.4 v v dd = 2.7 v to 3.63 v low, v inl 0.8 v v dd = 2.7 v to 3.63 v input current, i in 15 a v in = 0 v internal capacitance, c in 10 pf logic outputs miso, irq0 , and irq1 v dd = 2.97 v to 3.63 v output voltage high, v oh ? 2.4 v i source = 4 ma low, v ol 0.8 v i sink = 4 ma internal capacitance, c in 10 pf cf1, cf2, cf3, and cf4 v dd = 2.97 v to 3.63 v output voltage high, v oh 2.4 v i source = 8 ma low, v ol 0.8 v i sink = 8 ma internal capacitance, c in 10 pf
data sheet ade9078 rev. 0 | page 7 of 107 parameter min typ max unit test conditions/comments logic outputs miso, irq0 , and irq1 v dd = 2.7 v output voltage high, v oh ? 2.4 v i source = 1 ma low, v ol 0.8 v i sink = 4 ma cf1, cf2, cf3, and cf4 v dd = 2.7 v output voltage high, v oh 2.4 v i source = 3 ma low, v ol 0.8 v i sink = 8 ma low dropout regulators (ldos) avdd 1.9 v see the power-on sequence section dvdd 1.7 v power supply ? for specified performance vdd 2.7 3.3 3.63 v supply current (vdd) v dd = 3.63 v power save mode 0 (psm0) ? 10 12 ma normal mode, seven adcs enabled 9.5 11 ma normal mode, seven adcs enabled, total reactive power computation disabled 10.5 12 ma normal mode, seven adcs enabled, waveform buffer enabled 10 11.6 ma normal mode, six adcs enabled power save mode 1 (psm1) 9 10.6 ma fast rms, active power, and total reactive power measurement within 30 ms for tamper detection power save mode 2 (psm2) 115 200 a compares current to threshold, avdd = 0 v, dvdd = 0 v power save mode 3 (psm3) 50 200 na idle, avdd = 0 v, dvdd = 0 v 1 throughout this data sheet, multifunction pins, such as cf3/zx, ar e referred to either by the entire pin name or by a single f unction of the pin, for example, cf3, when only that function is relevant. 2 tested during device characterization. timing characteristics table 2. parameter symbol min typ max unit ss to sclk edge t ss 10 ns sclk frequency 10 mhz sclk low pulse width t sl 40 ns sclk high pulse width t sh 40 ns data output valid after sclk edge t dav 40 ns data input setup time before sclk edge t dsu 10 ns data input hold time after sclk edge t dhd 10 ns data output fall time t df 10 ns data output rise time t dr 10 ns sclk fall time t sf 10 ns sclk rise time t sr 10 ns miso disable after ss rising edge t dis 100 ns ss high after sclk edge t sfs 0 ns
ade9078 data sheet rev. 0 | page 8 of 107 msb lsb lsb in intermediate bits intermediate bits t sfs t dis t ss t sl t df t sh t dhd t dav t dsu t sr t sf t dr msb in mosi miso sclk ss 14331-002 figure 2. spi interface timing
data sheet ade9078 rev. 0 | page 9 of 107 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3 . parameter rating vdd to gnd ? 0.3 v to +3.96 v analog input voltage to gnd, iap, ian, ibp, ibn, icp, icn, vap, van vbp, vbn, vcp, vcn ? 1.9 v to +2 v reference input voltage to refgnd ? 0.3 v to +2 v digital input voltage to gnd ? 0.3 v to v dd + 0.3 v digital output voltage to gnd ? 0.3 v to v dd + 0.3 v operating temperature industrial range ?40c to +85c storage temperature range ?65c to +150c lead temperature (soldering, 10 sec) 1 260c esd human body model 2 4 kv machine model 3 200 v field induced charged device model (ficdm) 4 1.25 kv 1 analog devices recommends that reflow profiles used in soldering rohs compliant devices conform to j - std - 0 20 d.1 from jedec. refer to jedec for the latest revision of this standard . 2 a pplicable standard: ansi/esda/jedec js - 001- 2014. 3 applicable standard: jesd22 - a115 - a (esd machine model standard of jedec). 4 applicable standard jesd22 - c101f (esd ficdm standard of jedec). stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indic ated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance thermal performance is directly linked to printed circuit board (pcb) design and operating environment. careful attention to pcb thermal design is required. table 4 . thermal resistance package type ja jc unit cp -40-7 1 27.14 3.13 c/w 1 test condition 1: the j unction to a ir measurement use s a 2s2p jedec test board w ith 4 4 standard jedec vias. the j unction to c ase measurement use s a 1s0p jedec test board with 4 4 standard jedec vias. see jedec standard jesd51 - 2. esd caution
ade9078 data sheet rev. 0 | page 10 of 107 pin configuration and fu nction descriptions 1 pull_high 2 dgnd 3 dvddout 4 pm0 5 pm1 6 reset 7 iap 8 ian 9 ibp 10 ibn 23 vcn 24 vcp 25 avddout 26 agnd 27 vdd 28 gnd 29 clkin 30 clkout 22 vbp 21 vbn 1 1 i c p 1 2 i c n 1 3 i n p 1 5 r e f g n d 1 7 n c 1 1 6 r e f 1 8 n c 2 1 9 v a n 2 0 v a p 1 4 i n n 3 3 c f 1 3 4 c f 2 3 5 c f 3 / z x 3 6 c f 4 / e v e n t / d r e a d y 3 7 s c l k 3 8 m i s o 3 9 m o s i 4 0 s s 3 2 i r q 1 3 1 i r q 0 ade9078 top view (not to scale) 14331-003 notes 1. it is recommended to tie the nc1 and nc2 pins to ground. 2. exposed pad. create a similar pad on the printed circuit board (pcb) under the exposed pad. solder the exposed pad to the pad on the pcb to confer mechanical strength to the package and connect all grounds (gnd, agnd, dgnd, and refgnd) together at this point. figure 3. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 pull_high pull high. tie this pin to vdd. 2 dgnd digital ground. this pin provides the ground reference for the digital circuitry in the ade9078. because the digital return currents in the ade9078 are small, it is acceptable to connect this pin to the analog ground plane of the whole system. connect all grounds (gnd, agnd, dgnd, and refgnd) together at one point. 3 dvddout 1.8 v output of the digital low dropout regulator (l do). decouple this pin with a 0.1 f ceramic capacitor in parallel with a ceramic 4.7 f capacitor. 4 pm0 power mode pin 0. pm0, combined with pm1, defi nes the power mode. for normal operation, pm0 and pm1 must be grounded (see the power modes section). 5 pm1 power mode pin 1. pm1 combined with pm0, defi nes the power mode. for normal operation, pm0 and pm1 must be grounded (see the power modes section). 6 reset reset input, active low. this pin must stay low for at least 1 s to trigger a hardware reset. 7, 8 iap, ian analog inputs, channel ia. the iap (positive) and ian (negative) inputs are fully differential voltage inputs with a maximum differential level of 1 v. this channel also has an internal pga of 1, 2, or 4. 9, 10 ibp, ibn analog inputs, channel ib. the ibp (positive) and ib n (negative) inputs are fully differential voltage inputs with a maximum differential level of 1 v. this channel also has an internal pga of 1, 2, or 4. 11, 12 icp, icn analog inputs, channel ic. the icp (positive) and ic n (negative) inputs are fully differential voltage inputs with a maximum differential level of 1 v. this channel also has an internal pga of 1, 2, or 4. 13, 14 inp, inn analog inputs, channel in. the inp (positive) and in n (negative) inputs are fully differential voltage inputs with a maximum differential level of 1 v. this channel also has an internal pga of 1, 2, or 4. 15 refgnd ground reference, internal voltage reference. connect all grounds (gnd, agnd, dgnd, and refgnd) together at one point. 16 ref voltage reference. the ref pin provides access to the on-chip voltage reference. the on-chip reference has a nominal value of 1.25 v. an external reference of 1.2 v to 1.25 v can also be connected at this pin. in either case, decouple ref to refgnd with 0.1 f ceramic capacitor in parallel with a ceramic 4.7 f capacitor. after reset, the on-chip reference is enabled. to use the internal voltage reference with external circuits, a buffer is required. the full-scale values mentioned in this data sheet are for a voltage reference of 1.25 v. 17 nc1 no connection. it is recommended to tie this pin to ground. 18 nc2 no connection. it is recommended to tie this pin to ground.
data sheet ade9078 rev. 0 | page 11 of 107 pin no. mnemonic description 19, 20 van , vap analog inputs, channel va . the vap (positive) and van (negative) inputs are fully differential voltage inputs with a maximum differential level of 1 v. this channel also has an internal pga of 1, 2 , or 4 . 21, 22 vbn , vbp analog inputs, channel vb . the vbp (positive) and vbn (negative) inputs are fully differential voltage inputs with a maximum differential level of 1 v. this channel also has an internal pga of 1, 2 , or 4 . 23 , 24 vcn , vcp analog inp uts, channel vc . t he vcp (positive) and vcn (negative) inputs are fully differential voltage inputs with a maximum differential level of 1 v. this channel also has an internal pga of 1, 2 , or 4 . 25 avddout 1.9 v output of the analog low dropout regulator (ldo). decouple a vddout with a 0.1 f ceramic capacitor in parallel with a ceramic 4.7 f capacitor . do not connect external active circuitry to this pin. 26 agnd analog ground reference . c onnect all grounds ( gnd, agnd, dgnd, and refgnd ) together at one point. 27 vdd supply voltage. the vdd pin provides the supply voltage. decouple vdd to gnd with a ceramic 0.1 f capacitor in parallel with a ceramic 10 f capacitor. 28 gnd supply ground reference. c onnect all grounds ( gnd, agnd, dgnd, and refgnd ) together at one point. 29 clkin c rystal/ c lock i nput . connect a crystal across clkin and clkout to provide a clock source . see the crystal selection section for details on choosing a suitable crystal. alternatively, an external clock can be provided at this logic input. 30 clkout crystal output. connect a crystal across clkin and clkout to provide a clock source. w hen using clkout to drive external circuits, c onnect an external buffer . when using an external clock on clkin, leave clkout unconnected. 31 irq0 interrupt request output. th is pin is a n active low logic output. see the interrupts/e vents section for information about events that trigger interrupts. 32 irq1 interrupt request output. th is pin is a n active low logic output . see the interrupts/e vents section for information about events that trigger interrupts. 33 cf1 calibration frequency (cf) logi c ou tput 1 . the cf1, cf2, cf3 , and cf4 outputs provide power information based on the cfxsel bits in t he cfmode register. use these out puts for operational and calibration purposes. scale the full - scale output frequency by writing to the cfxden registers ( see the digital to frequency conve rsion cfx output section). 34 cf2 cf logic output 2. this pin i ndicate s cf2 . 35 cf3/zx cf logic output 3/zero crossing. t his pin indicate s cf3 or zero crossing . 36 cf4/ event /dready cf logic output 4/event pin/data ready. this pin indicate s cf4, events , or when new data is ready . 37 sclk serial clock input for the spi port. all serial data transfers synchronize to this clock (see the accessing on - c hip data section). the sclk pin has a schmitt trigger input for use with a clock source that has a slow edge transition time, for example, optoisolator outputs. 38 miso data output for the spi port . 39 mosi data input for the spi port . 40 ss slave select for the spi port . ep exposed pad. create a similar pad on the printed circuit board (pcb) under the exposed pad. solder the exposed pad to the pad on the pcb to confer mechanical strength to the package and connect all grounds ( gnd, agnd, dgnd, and refgnd ) together at this point.
ade9078 data sheet rev. 0 | page 12 of 107 typical performance characteristics total energy lineari ty over supply and t emperature s inusoidal voltage with an amplitude of 50% of full scale and a frequency of 50 hz; sinusoidal current with variable amplitudes from 100% of full scale down to 0.005% or 0.02% of full scale and with a frequency of 50 hz; i ntegrator off . C0.5 C0.3 C0.1 0 0.1 0.3 0.5 0.001 0.01 0.1 1 10 100 error (%) percen t age of full-scale current (%) t a = C40c t a = +25c t a = +85c 14331-103 figure 4. total active energy error as a percentage of reading over temperature, pf = 1 0.001 0.01 0.1 1 10 100 error (%) percen t age of full-scale current (%) t a = C40c t a = +25c t a = +85c 14331-104 5 0 C0.5 C0.3 C0.1 0 0.1 0.3 0.5 0.01 0.1 1 10 100 error (%) percen t age of full-scale current (%) t a = C40c t a = +25c t a = +85c 14331-105 6 1 C0.5 C0.3 C0.1 0.1 0 0.3 0.5 0.001 0.01 0.1 1 10 100 error (%) percen t age of full-scale current (%) t a = 25c 2.7v 2.97v 3.3v 3.63v 14331-106 7 1 25 C0.5 C0.3 C0.1 0 0.1 0.3 0.5 0.001 0.01 0.1 1 10 100 error (%) percen t age of full-scale current (%) t a = 25c 2.7v 2.97v 3.3v 3.63v 14331-107 8 0 25 C0.5 C0.3 C0.1 0 0.1 0.3 0.5 0.01 0.1 1 10 100 error (%) percen t age of full-scale current (%) t a = 25c 2.7v 2.97v 3.3v 3.63v 14331-108 9 1 25
data sheet ade9078 rev. 0 | page 13 of 107 fundamental energy l in earity with fifth ha rmonic over supply a nd temperature f undamental voltage component in phase with fifth harmonic; current with a 50 hz component that has variable amplitudes from 1 00% of full scale down to 0.005% of full scale and a fifth harmonic with a constant amplitude of 40% of fundamental ; i ntegrator off . C0.5 C0.3 C0.1 0 0.1 0.3 0.5 0.001 0.01 0.1 1 10 100 error (%) percen t age of full-scale current (%) 14331-109 t a = C40c t a = +25c t a = +85c figure 10 . fundamental reactive energy error as a percentage of reading over temperature, pf = 0 0.001 0.01 0.1 1 10 100 error (%) percen t age of full-scale current (%) C0.5 C0.3 C0.1 0 0.1 0.3 0.5 t a = 25c 2.7v 2.97v 3.3v 3.63v 14331- 1 10 11 0 25
ade9078 data sheet rev. 0 | page 14 of 107 total energy error over frequency sinusoidal voltage with a constant amplitude of 50% of full scale; sinusoidal current with a constant amplitude of 10% of full scale; variable frequency between 45 hz and 65 hz; integrator off. 40 45 50 55 60 65 70 error (%) line frequency (hz) power factor = 1 power factor = 0.5 power factor = ?0.5 14331-111 figure 12. total active energy error as a percentage of reading vs. line frequency, pf = ?0.5, +0.5, and +1 ?0.10 ?0.05 0 0.05 0.10 40 45 50 55 60 65 70 error (%) line frequency (hz) power factor = 0 power factor = 0.866 power factor = ?0.866 14331-112 figure 13. total reactive energy error as a percentage of reading vs. line frequency, pf = ?0.866, 0, and +0.866
data sheet ade9078 rev. 0 | page 15 of 107 rms li nearity over tempera ture and rms e rror o ver frequency s inusoidal current and voltage with variable amplitudes from 100% of full scale down to 0.02% of full scale using a frequency of 50 hz; variable frequency between 45 hz and 65 hz; sinusoidal current amp litude of 10% of full scale and voltage amplitude of 50% of full scale ; i ntegrator off . C0.5 C0.3 C0.1 0.1 0 0.3 0.5 0.01 0.1 1 10 100 error (%) percen t age of full-scale current (%) t a = C40c t a = +25c t a = +85c 14331- 1 13 figure 14 . current rms error as a percentage of reading over temperature C0.5 C0.3 C0.1 0.1 0 0.3 0.5 0.01 0.1 1 10 100 error (%) percen t age of full-scale current (%) t a = C40c t a = +25c t a = +85c 14331- 1 14 15 40 45 50 55 60 65 70 error (%) line frequenc y (hz) 14331- 1 15 16 40 45 50 55 60 65 70 error (%) line frequenc y (hz) 14331- 1 16 17
ade9078 data sheet rev. 0 | page 16 of 107 energy linearity rep eatability s inusoidal voltage with an amplitude of 50% of full scale and a frequency of 50 hz; sinusoidal current with variable amplitudes from 100% of full scale down to 0.005% of full scale and with a frequency of 50 hz . for figure 20 , be sides the fundamental component, the voltage contained a fifth harmonic with a constant amplitude of 40% of fundamental, and the current contained a fifth harmonic with a constant amplitud e of 40% of fundamental. integrator off . measurements at 25c repeated 30 times. C0.5 C0.3 C0.1 0 0.1 0.3 0.5 0.001 0.01 0.1 1 10 100 error (%) percen t age of full-scale current (%) 14331- 1 17 figure 18 . total active energy error as a percentage of reading, pf = 1 (standard deviation = 0.03% at 0.01% of full - s cale current) C0.5 C0.3 C0.1 0.1 0 0.3 0.5 0.001 0.01 0.1 1 10 100 error (%) percen t age of full-scale current (%) 14331- 1 18 19 0 004 001 - C0.5 C0.3 C0.1 0.1 0 0.3 0.5 0.001 0.01 0.1 1 10 100 error (%) percen t age of full-scale current (%) 14331- 1 19 20 0 004 001 -
data sheet ade9078 rev. 0 | page 17 of 107 total energy and rms linear ity with integrator on sinusoidal voltage with an amplitude of 50% of full scale and a frequency of 50 hz; gain of current channel set to 4; sinusoida l current with variable amplitudes from 100% of full scale down to 0.05% or 0.1% of full scale and with a frequency of 50 hz; full scale at gain of 4 = (full scale at gain of 1)/4, high-pass corner frequency of 4.97 hz. ?0.5 ?0.3 ?0.1 0.1 0 0.3 0.5 0.01 0.1 1 10 100 error (%) percentage of full-scale current (%) power factor = 1 power factor = 0.5 power factor = ?0.5 14331-120 figure 21. total active energy error, gain = 4, integrator on ?0.5 ?0.3 ?0.1 0.1 0 0.3 0.5 0.1 1 10 100 error (%) percentage of full-scale current (%) 14331-121 figure 22. total reactive energy error, gain = 4, integrator on ?0.5 ?0.3 ?0.1 0.1 0 0.3 0.5 0.01 0.1 1 10 100 error (%) percentage of full-scale current (%) power factor = 0 power factor = 0.866 power factor = ?0.866 14331-122 figure 23. total apparent energy error, gain = 4, integrator on ?0.5 ?0.3 ?0.1 0.1 0.3 0.5 0.1 1 10 100 percentage of full-scale current (%) error (%) 14331-123 figure 24. total rms current error, gain = 4, integrator on
ade9078 data sheet rev. 0 | page 18 of 107 total energy error o ver frequency with i ntegrator o n s inusoidal voltage with a constant amplitude of 50% of full scale; g ain of current channel set to 4; sinusoidal current with a constant amplitude of 10% of full scale; variable frequency between 45 hz and 65 hz , g igh- pass corner frequency of 4.97 hz . power f ac t or = 0 power f ac t or = 0.5 power f ac t or = C0.5 40 45 50 55 60 65 70 error (%) line frequenc y (hz) 14331-124 figure 25 . total active energy error as a percentage of reading vs. line frequency, gain = 4, integrator o n 40 45 50 55 60 65 70 error (%) line frequenc y (hz) power f ac t or = 0 power f ac t or = 0.866 power f ac t or = C0.866 14331-125 26 4
data sheet ade9078 rev. 0 | page 19 of 107 test circuit same as cf2 pm0 0.22f 4.7f mosi miso cf4/event/dready cf3/zx cf2 cf1 ref in/out clkout clkin pm1 reset iap ian ibp ibn icp icn inp inn vbn vbp 4 22 5 6 7 8 9 10 11 12 13 14 21 40 39 38 36 35 34 33 32 31 16 30 29 ade9078 25 27 3 avddout vdd dvddout 2 15 dgnd agnd 0.22f 4.7f 0.1f 4.7f + + + 0.1f 10f + same as iap, ian same as iap, ian 22nf 1k ? 1k ? 1k ? 10k ? 1k ? 22nf 3.3v 3.3 v 1f 22nf 22nf ss irq1 irq0 3.3v 18pf 18pf same as iap, ian van vap 20 19 same as vap, van vcn 24 23 same as vap, van vcp sclk 37 26 28 refgnd gnd 14331-127 figure 27. test circuit
ade9078 data sheet rev. 0 | page 20 of 107 terminology differential input voltage range and maximum operating voltage on vxp, vxn, ixp, and ixn analog input pins the differential input range describes the maximum difference between the ixp and ixn or vxp and vxn pins. the maximum operating voltage given in table 1 describes the maximum voltage that can be present on each pin, including any common- mode voltage. figure 28 illustrates the maximum input between xp and xm, which is seen in the application when a current transformer with center tapped burden resistor is used. figure 29 illustrates the maximum input voltage range between xp and xn when a pseudo differential input is applied, as is commonly seen when sensing the line voltage. +0.1v 0 +0.6v ?0.4v 0x0474 e650 = +74,770,000 0xfb8b 19b0 = ?74,770,000 channel (x_pcf) waveform data range with x_gain = 1 xp input pin xm input pin +0.1v +0.6v ?0.4v 14331-010 figure 28. maximum input signal with differential antiphase input with common-mode voltage = 0.1 v gain = 1 +0.1v 0 +0.6v -0.4v +0.1v 0x0474 e650 = +74,770,000 0xfb8b 19b0 = ?74,770,000 channe l (x_pcf) waveform data range with x_gain = 2 xp input pin xm input pin 14331-011 figure 29. maximum input signal wi th pseudo differential input with common-mode voltage = 0.1 v, gain = 2 (x_gain = 2) crosstalk crosstalk is measured by grounding one channel and applying a full-scale 50 hz or 60 hz signal on all the other channels. the crosstalk is equal to the ratio between the grounded adc output value and its adc full-scale output value. the adc outputs are acquired for 100 sec. crosstalk is expressed in decibels. differential input impedance (dc) the differential input impedance represents the impedance between the pair ixp and ixn or vxp and vxn. it varies with the pga gain selection as indicated in table 1. adc offset adc offset is the difference between the average measured adc output code with both inputs connected to gnd and the ideal adc output code of zero. adc offset is expressed in microvolts. adc offset drift over temperature the adc offset drift is the change in offset over temperature. it is measured at ?40c, +25c, and +85c. the offset drift over temperature is computed as follows: ?? ?? ?? ?? ?? ?? ? ? ? ? ? ? ? ? ??? ??? ???? ???? ? c25c85 c25 c85 , c25c40 c25 c40 max offset offset offset offset drift offset drift is expressed in v/c. gain error the gain error in the adcs represents the difference between the measured adc output code (minus the offset) and the ideal output code when an external voltage reference of 1.2 v is used (see the voltage reference section). the difference is expressed as a percentage of the ideal code. it represents the overall gain error of one channel. gain drift over temperature this temperature coefficient includes the temperature variation of the adc gain while using an external voltage reference of 1.2 v. it represents the overall temperature coefficient of one current or voltage channel. with an external voltage reference of 1.2 v in use, the adc gain is measured at ?40c, +25c, and +85c. then the temperature coefficient is computed as follows: ?? ?? ?? ?? ?? ?? ? ? ? ? ? ? ? ? ????? ??? ?????? ???? ? c25c85c)25( c25 c85 , c25c40c)25( c25 c40 max gain gain gain gain gain gain drift gain drift is measured in ppm/c.
data sheet ade9078 rev. 0 | page 21 of 107 ac power supply rejection (psr r ) ac psr r quantifies the measurement error as a percentage of reading when the dc power supp ly is v nom and modulated with ac a nd the inputs are grounded. for the ac psrr measurement, 20 s ec of samples is captured with nominal supplies (3.3 v) and a second set are captured with an additional ac signal (330 mv p ea k at 50 hz ) introduced onto the supplies. then , the psrr is expressed as psr r = 20 log 10 ( v2/v1 ). signal -to - noise ratio (snr) snr is calculated by inputting a 50 hz signal, and samples are acquired for 2 sec . the amplitudes for each frequency u p to the bandwidth given in table 1 as the adc o utput b andwidth (?3 db) are calculated. to determine the snr, the signal at 50 hz is compared to the sum of the power from all the other frequencies , removing power from its harmo nics. the value for snr is expressed in decibels. signal -to - noise - and - distortion ratio (sinad) sinad is calculated by inputting a 50 hz signal, and samples are acquired for 2 sec . the amplitudes for each frequency up to the bandwidth given in table 1 as the adc o utput b andwidth (?3 db) are calculated. to determine the sinad, the signal at 50 hz is compared to the sum of the power from all the other frequencies. the value for sinad is expr essed in decibels. total harmonic distortion ( thd ) thd is calculated by inputting a 50 hz signal, and samples are acquired for over 2 sec . the amplitudes for each frequency up to the bandwidth given in table 1 as the adc o utput b andwidth (?3 db) are calculated. to determine the thd, the amplitudes of the 50 hz harmonics up to the bandwidth are root sum squared . the value for thd is expressed in decibels. spurious - free dynamic range ( sfdr ) sfdr is calculated by inputting a 50 hz signal, and samples are acquired for over 2 sec . t he amplitudes for each frequency up to the bandwidth given in table 1 as the adc output bandwidth (?3 db) are calculated. to determine the sfdr, the amplitude of the largest signal that is not a harmonic of 50 hz is recorded. the value for sfdr is expressed in decibels. adc output pass b and the adc output pass band is the bandwidth within 0.1 db, resulting from the digital filtering in the sinc4 and sinc4 + iir l pf. adc output bandwidth the adc output bandwidth is the bandwidth within ? 3 db, resulting from the digital filtering in the sinc4 and sinc4 + iir lpf .
ade9078 data sheet rev. 0 | page 22 of 107 theory of operation the ade9078 integrates seven high performance adcs and a flexible dsp core. an integrated high end reference ensures low drift over temperature with a combined drift of less than 25 ppm/c maximum for the whole channel including pga and adc. the ade9078 is a highly accurate, fully integrated energy metering device. interfacing with both ct and rogowski coil sensors, the ade9078 enables users to develop a 3-phase metrology platform, which achieves high performance for class 1 through class 0.2 meters. see the measurements (normal mode) section for more information. two power modes are provided to enable detection of meter tampering: psm2 uses a low power comparator to compare current channels to a threshold and indicates whether it has been exceeded on the irq0 and irq1 outputs; psm1 enables fast measurement of current and voltage rms (xvrms, xirms), active power, and var during a tamper. see the measurements (psm1) section and measurements (psm2) section for more information about how to use these modes. adc overview the ade9078 incorporates seven independent, second-order, - adcs that sample simultaneously. each adc is 24 bits and supports fully differential and pseudo differential inputs that can go above and below ground. the ade9078 includes a low noise, low drift, internal band gap reference. set the ext_ref bit in the config1 register if using an external voltage reference. each adc contains a programmable gain amplifier, which allows a gain of 1, 2, or 4. the adcs incorporate proprietary dither techniques to prevent idle tones at low input levels, extending the accuracy range. analog input configuration there is no internal buffering on the device. the impedance of the ade9078 depends on the programmable gain selected (see the specifications table). fully differential inputs the input signals on the iap, ian, ibp, ibn, icp, icn, vap, van, vbp, vbn, vcp, and vcn pins must not exceed 0.6 v relative to agnd, the analog ground reference. the differential full- scale input range of the adcs is 1 v peak (0.707 v rms), and the maximum allowed common-mode voltage at the adc pins must not exceed 0.1 v. figure 30 and figure 31 show two common types of input signals for an energy metering application. figure 30 shows the maximum input allowed with differential antiphase signals. a current transformer with center tapped burden resistor generates differential antiphase signals. figure 31 shows the maximum input signal with pseudo differential signals, similar to those obtained when sensing the mains voltage signal through a resistive divider or using a rogowski coil current sensor. the following conditions must be met for the input signals with gain = 1: ? |iap, ian, ibp, ibn, icp, icn, vap, van, vbp, vbn, vcp, and vcn| 0.6 v peak relative to agnd ? |ixp ? ixn| 1 v peak, |vxp ? vxn| 1 v peak +0.1v 0 +0.6v ?0.4v 0x0474 e650 = notes 1. x_pcf is the instantaneous waveform obtained after gain and phase compensation. +74,770,000 0xfb8b 19b0 = ?74,770,000 channel (x_pcf) waveform data range with x_gain = 1 xp input pin xm input pin +0.1v +0.6v ?0.4v 14331-012 figure 30. maximum input signal with differential antiphase input with common-mode voltage = 0.1 v, gain = 1 +0.1v 0 +0.6v ?0.4v +0.1v 0x0474 e650 = +74,770,000 xfb8b 19b0 = ?74,770,000 channel (x_pcf) waveform data range with x_gain = 2 xp input pin xm input pin 14331-013 n otes 1 . x_pcf is the instantaneous waveform obtained after gain and phase compensation. figure 31. maximum input signal wi th pseudo differential input with common-mode voltage = 0.1 v, gain = 2 each adc contains a programmable gain amplifier that allows a gain of 1, 2, or 4. the adc produces full-scale output codes with an input of 1 v. with a gain of 1, this full-scale input corresponds to a differential antiphase input of 0.707 v rms, as shown in figure 30. at a gain of 2, full-scale output codes are produced with an input of 0.353 v rms, as shown in figure 31. at a gain
data sheet ade9078 rev. 0 | page 23 of 107 of 4, full-scale output codes are generated with a 0.1765 v rms input signal. note that the voltages on the xp and xn pins must be within 0.6 v as described in this section and table 1. write the x_gain bits in the pga_gain register to configure the gain for each channel. interfacing to current and voltage sensors figure 32 and figure 34 show the typical circuits to connect to current transformer and rogowski coil current sensors. figure 33 shows the typical interface circuit to measure the mains voltage. the antialiasing filter corner is chosen to be around 7 khz to provide sufficient attenuation of out of band signals near the modulator clock frequency. the same rc filter corner is used on voltage channels, as well, to avoid phase errors between current and voltage signals. note that the rogowski coil (that is, a di/dt sensor) input network has a second-order antialiasing filter. the integrator used in conjunction to the rogowski coil has a ?20 db/dec attenuation and an approximately ?90 phase shift. when combined with a di/dt sensor, the resulting magnitude and phase response is a flat gain over the frequency band of interest. however, the di/dt sensor has a 20 db/dec gain associated with it, and it generates significant high frequency noise. an antialiasing filter of at least the second order is required to avoid noise aliasing back in the band of interest when the adc is sampling. see figure 34 for the recommended antialiasing filter. 1k ? 8.2 ? 22nf agnd ixp ixn 0.656v rms max 100a rms max 10a rms nom ct i 8.2 ? 1k ? 22nf agnd 2500:1 14331-014 figure 32. application circuit with a current transformer current sensor 1m ? 1k ? 22nf agnd vxp vxn 0.240v rms 240v rms 1k ? 22nf neutral phase agnd 14331-015 figure 33. application circuit with vo ltage sensed through resistor divider 1k ? ixp ixn 0.3535v rms 22nf 22nf 100 ? 1k ? 22nf 22nf 100 ? 14331-016 figure 34. application circuit with rogowski coil current sensor internal rf immunity filter energy metering applications require the meter to be immune to external radio frequency fields of 30 v/m, from 80 mhz to 10 ghz, according to iec 61000-4-3. the ade9078 has internal antialias- ing filters to improve performance in testing because it is difficult to filter these signals externally. the second-order, internal low- pass filter has a corner frequency of 10 mhz. note that external antialias filters are required to attenuate frequencies above 7 khz, as shown in the interfacing to current and voltage sensors section. modes of operation each adc has two modes of operation: normal mode and disabled mode. in the normal mode, the adcs turn on and sample continuously. use the chnl_dis register to disable the adcs individually. four different power modes are available in the ade9078 (see the power modes section). all adcs turn on during the psm0 power mode. in the psm1 power mode, all of the adcs except for the neutral current adc are turned on. in psm2 mode and psm3 mode, all adcs are disabled and cannot be turned on. table 6. adc operation in psmx power modes psmx power mode adc mode of operation psm0 normal (on) psm1 ia, ib, ic, va, vb, vc: normal (on) in: disabled (always off) psm2 disabled (always off) psm3 disabled (always off) output data rates and format when a conversion is complete, the dready bit of the status0 register is set to 1. if the cf4_cfg bits in the config1 register are equal to 11, the cf4/ event /dready pin corresponds to dready and pulses high to indicate when seven new adc results are ready. note that the dready update rate depends on the data selected in the wf_src bits in the wfb_cfg register. for the ade9078 , the modulator sampling rate (modclk) is fixed at 1.024 mhz (clkin/12 = 12.288 mhz/12). the output data rate of the sinc4 filter is 16 khz (sinc_odr = modclk/64), whereas the low-pass filter/decimator stage yields an output rate four times slower than the sinc4 filter output rate (sinc_odr). figure 35 shows the digital filtering, which takes the 1.024 mhz adc samples and creates waveform information at a decimated rate of 16 khz or 4 khz. analog input - ? 7 digital multibit sinc4 iir lpf/ decimator digital waveform waveform buffer (7 channels) 1.024mhz 16khz 4khz 14331-017 figure 35. datapath following adc stage
ade9078 data sheet rev. 0 | page 24 of 107 the output data rates are summarized in table 7. table 7. output data rates parameter data rate clkin frequency 12.288 mhz adc modulator clock, modclk 1.024 mhz sinc4, sinc_odr 16 khz low-pass filter 4 khz bandwidth (pass band) 0.672 khz the adc data in the waveform buffer is stored as 32-bit data by shifting left by 4 bits and sign extending, as shown in figure 36. adc_data[23:0] 0000 se 14331-136 figure 36. format for the adc data stored in the waveform buffer, x_sinc_dat and x_lpf_dat registers the expected output code from the sinc4 filter when input is at 1 v peak is 4,190,000 decimal (d), which corresponds to a value of 67,110,000d in the waveform buffer. the expected output code from the decimator filter when input is at 1 v peak is 4,660,000d, which corresponds to a value of 74,520,000d in the waveform buffer (see the waveform buffer section for more information). voltage reference the ade9078 supports a 1.25 v internal reference. the temperature drift of the reference voltage is 5 ppm/c typical, 20 ppm/c maximum. an external reference can be connected between the ref and refgnd pins. set the ext_ref bit of the config1 register when using an external voltage reference, which disables the internal reference buffer. crystal oscillator/external clock the ade9078 contains a crystal oscillator. alternatively, a digital clock signal can be applied at the clkin pin of the ade9078 . when a crystal is used as the clock source for the ade9078 , attach the crystal and the ceramic capacitors, with capacitances of c l1 and c l2 , as shown in figure 37. it is not recommended to attach an external feedback resistor in parallel to the crystal. when a digital clock signal is applied at the clkin pin, the inverted output is available at the clkout pin. this output is not buffered internally and cannot drive any other external devices directly. note that clkout is available in the psm0 and psm1 operating modes only. p1 l1 clkin clkout 29 30 p2 l2 1.75k ? 2.5k ? c in1 c in2 12.288mhz 14331-018 figure 37. crystal application circuit crystal selection the transconductance of the crystal oscillator circuit in the ade9078 , g m , is provided in table 1. it is recommended to have three to five times more g m than the calculated g mcritical for the crystal. the following equation shows how to calculate the g mcritical for the crystal from information given in the crystal data sheet: g mcritical = 4 esr max 1000 (2 f clk (hz) ) 2 ( c0 + c l ) 2 where: g mcritical is the minimum gain required to start the crystal in ma/v. esr max is the maximum electrical series resistance (esr), expressed in . f clk (hz) is 12.288 mhz, expressed in hz as 12.288 10 6 . c0 is the maximum shunt capacitance, expressed in farads. c l is the total load capacitance, expressed in farads. crystals with low esr and smaller load capacitance have a lower g mcritical and are easier to drive. the evaluation board of the ade9078 uses a crystal manufactured by abracon (abls-12.288mhz-l4q-t), which has a maximum esr of 50 , a load capacitance of 18 pf, and a maximum shunt capacitance of 7 pf, which results in a g mcritical of 0.75 ma/v, as follows: g mcritical = 4 esr max 1000 (2 f clk (hz) ) 2 ( c0 + c l ) 2 g mcritical = 4 50 1000 (2 12.288 10 6 ) 2 (7 10 ?120 + 18 10 ?12 ) 2 = 0.75 ma/v the gain of the crystal oscillator circuit in the ade9078 , the g m , provided in table 1 is more than 5 g mcritical ; thus, there is sufficient margin to start up this crystal. load capacitor calculation crystal manufacturers specify the combined load capacitance across the crystal, c l . the capacitances in figure 37 can be described as follows: ? c p1 and c p2 are the parasitic capacitances on the clock pins formed due to pcb traces. ? c in1 and c in2 are the internal capacitances of the clkin and clkout pins, respectively. ? c l1 and c l2 are the selected load capacitors to reach the correct combined c l for the crystal. the internal pin capacitances, c in1 and c in2 , are 4 pf each, as given in table 1. to find the values of c p1 and c p2 , measure the capacitance on each of the clock pins of the pcb, clkin, and clkout, respectively, with respect to the agnd pin. if the measurement is performed after soldering the ic to the pcb, subtract the 4 pf internal capacitance of the clock pins to determine the actual value of parasitic capacitance on each of the crystal pins.
data sheet ade9078 rev. 0 | page 25 of 107 to select the appropriate capacitance value for the ceramic capacitors, cal culate c l 1 and c l 2 , from the following expression: c l = ( ( c l1 + c p1 + c in1 ) ( c l2 + c p2 + c in2 ) )/( c l1 + c p1 + c in1 + c l2 + c p2 + c in2 ) (1) select c l1 and c l2 such that the total capacitance on each clock pins is equal: c l1 + c p1 + c in1 = c l2 + c p2 + c in2 (2) using equation 1 and equation 2, the values of c l 1 and c l 2 can be calculated. load capacitor calculation example if a crystal with load capacitance specification of 12 pf is selected, and the measured parasitic capacit ances from the pcb traces are c p 1 = c p 2 = 2 pf , e quation 1 implies, c l = ( ( c l1 + c p1 + c in1 ) ( c l2 + c p2 + c in2 ) ) /( c l1 + c p1 + c in1 + c l2 + c p2 + c in2 ) 12 pf = (( c l1 + 2 pf + 4 pf) ( c l2 + 2 pf + 4 pf))/( c l1 + 2 pf + 4 pf + c l2 + 2 pf + 4 pf) assuming c l 1 = c l 2 , to satisfy e quation 2, 12 pf = (( c l1 + 6 pf) ( c l1 + 6 pf))/( c l1 + 6 pf + c l1 + 6 pf) 12 pf = ( ( c l1 + 6 pf) ( c l1 + 6 pf) ) /(2 ( c l1 + 6 pf)) 12 pf = ( c l1 + 6 pf)/2 thus, c l 1 = c l 2 = 18 pf . based on this example, 18 pf ceramic capacitors are selected for c l1 and c l2 . the user must verify the customized values based on care - ful investigations on multiple devices over the t emperature range. power management power mode s the ade9078 offers four operating mod es: psm0, psm1, psm2 , and psm3. the entry into the power modes is controlled by the pm1 and pm0 pins. these pin s are checked continuously to determine which operating mode to enter. table 8 shows the pmx pin configurations for each power mode. most applicati ons use psm0 (normal mode). if the user wants to put the ade9078 into a low power reset state, use psm 3. psm1 and psm2, in combination with psm3, enable low power tamper detection and measurement, which is required in some regions. these operating modes enable the user to check for a tamper condition while minimizing p ower consumption because in tamper scenarios , a battery typically power s the ade9078 . the current peak detect ion mode, psm2, checks if the input currents a re above a user set amplitude. the t am per m easurement m ode, psm1, allows the user to make key measurements quickly for irms, vrms, active power , a n d va r with a reduced power consumption compared to psm0. in the application, the host microcontroller creates a duty cycle that puts the ade9078 into psm2, waits the required time to receive a result indicated in table 8 , and then returns to psm3. this cycle continues once per minute until the tamper checking cycle e nds, which may be up to seven days in some applications. if a tamper is detected in psm2, psm1 is entered and the key measure - ments are made. after the time r equired for measurements has elapsed, the host microcontroller reads the results via the spi interface and changes the pm1 and pm0 pins to put the device back into psm3. this cycle continues once per minute until the tamper checking cycle ends , which may b e up to seven days in some applications . figure 38 shows the functions available in psm2 and psm1. sinc4 and decim a tion a vdd ldo dvdd ldo spi 1.25v reference temp sensor cf1 to cf4 irq0 irq1 spi pm1 pm0 ade9078 pga adc pga adc sar av ailable in psm0 av ailable in psm2 disabled in psm1 pga adc pga adc pga adc pga adc pga adc metrology features (per phase) irms, vrms active power, va yx, angle waveform buffer energy/power/cf accumul a tion line frequency etc. low power com p ara t or 14331-019 figure 38 . functions ava ilable in psm1 and psm2 as indicated in table 8 , the spi is not available in psm2. to check whether the current inputs are above the user configured tamper threshold, check the irq0 and irq1 pins (see th e measurements (psm2) section for more information ) . o ne register is retained during psm2 and psm3 : psm2_cfg, as shown in table 8 . note that if psm0 or psm1 is entered, psm2_cfg returns to it default value and must be rewritten before reentering p sm2 (see the measurements (normal mode) section, measurements (psm1) section , and measurements (psm2) section for details on functionality in psm0, psm1 , and psm2 ) .
ade9078 data sheet rev. 0 | page 26 of 107 table 8 . power modes (psm0, psm1, psm2 , and psm3) psmx power mode description pm1 pin pm0 pin power consumption functions available spi available retained registers when switching into power mode psm0 normal mode 0 0 10 ma all functions. yes not applicable psm1 tamper measurement mode 0 1 9 ma active and reactive power, irms, vrms, all calculated using the psm1 computation method. zx, period, and angle measurements are available . t he neutral current channel, waveform buffer, and energy/power/cf accumulations are disabled. yes not applicable psm2 current peak detect mode 1 0 115 a current peak detect. no psm2_cfg psm3 idle 1 1 50 na none. no psm2_cfg power - on sequence host configures ic vi a spi and then writes run register t o s t art measurements 20ms 0.5ms 0 vo lt age (v) ~26ms ade9078 rstdone interrupt triggered c r yst a l oscill a t or st arts por timer turned on a vdd, dvdd ldo turned on power applied t o ic in psm0, psm1 14331-020 figure 39 . po wer - o n sequence for psm0 and psm1 after power is applied to the vdd pin of the ade9078 , the device checks the state of the pm0 and pm1 pins to check the power supply mode (see the power mode s section for more information ) . if in psm1 or psm0 (pm1, pm0 = 00 or 01) and if the reset pin is high, the avdd and dvdd ldos turn on afte r vdd reaches 2.4 v to 2.6 v. i f t h e reset pin is low, the av dd and dvdd ldos are not turned on. note that a clamp l imits the current used to charge the avdd and dvdd ldos to approximately 17 ma per ldo. the power supply sourc e must be ab le to handle approximate charge current of 40 ma. when avdd and dvdd are both above 1.3 v to 1.5 v and vdd is above 2.4 v to 2.6 v, a 20 ms timer is started to allow additional time for the supplies to reach their normal potentials (vdd between 2.7 v and 3.6 v, avdd at 1.9 v, and dvdd at 1.7 v). after this timer has elapsed, the crystal oscillator start s. the rstdone interrupt is triggered approximately 26 ms later, bringing the irq1 pin low and setting the rstdone bit in the status1 reg ister. this rstdone interrupt indicates to the user that the ade9078 has finished its power - up sequence. then , the user can configure the ic via the spi (see the quick start section for a list of important registers to con f igure). after configuring the device, write the run register to start the dsp so that it starts making measurements. note that registe rs from address 0x000 through address 0x0ff and address 0x400 through address 0x5ff are restored to their default values during power - on. registers from address 0x200 through address 0x3ff are cleared within 500 s from when the run register value changes from 0x0000 to 0x0001. also note that the w aveform b uffer, address 0x800 through address 0xff f , is not cleared after reset. in psm2 and psm3, the avdd and dvdd ldos are not turned on. the rstdone interrupt does not occur and the spi port is not available (see the power mode s section for more information on these modes ) . brownout detection power - on reset (por) circuits monitor the vdd, avdd, and dvdd supplies. if avdd or dvdd drop below a threshold between 1.3 v and 1.5 v, or vdd drops below a threshold betwee n 2.4 v and 2.6 v, the ic is held in reset. if the power - on sequence begins again, the ade9078 waits until avdd and dvdd are above 1.3 v to 1.5 v and vdd is above 2.4 v to 2.6 v to start t he 20 ms por timer. a rstdone interrupt on the irq1 pin indic ates when the ade9078 can be reinitialized via spi.
data sheet ade9078 rev. 0 | page 27 of 107 reset if the reset pin goes low for 1 s, the avdd and dvdd ldos turn off. the power on sequence resumes from the point where the avdd and dvdd ldos are turned on (see the power-on sequence section for details). a software reset is initiated by writing the swrst bit in the config1 register, which resets the digital logic and takes ~60 s to complete. for applications that require putting the ade9078 into a low power mode, it is recommended to use psm3. in this mode, the ade9078 consumes approximately 2 a, much lower than the 100 a current consumption obtained when the ade9078 reset pin is held low (see table 1 for the exact psm3 current consumption). changing to psm2 or psm3 the state of the pm1 and pm0 pins is continuously monitored. if the power mode changes from psm0 or psm1 to psm2 or psm3 (pm1, pm0 = 10 or 11) for 1 s, the avdd and dvdd ldos are turned off. when the power mode switches back to psm0 or psm1, the power on sequence resumes from the point where avdd and dvdd ldos are turned on (see the power- on sequence section for details). measurements (normal mode) the ade9078 offers per phase total irms and vrms as well as total active power, var, va, and fundamental var powers. the instantaneous low-pass filtered powers can be accumulated into power or energy registers and are available in pulsed outputs, cf1 through cf4. power quality information, such as zero-crossing detection, line period, and angle measurements, is also available. a waveform buffer stores samples directly from the adc, calculated resampled data, or processed current and voltage samples. the measurements described are available in psm0, the normal operating mode. a reduced set of features is available in psm1 and psm2 (see the power modes section for more details on these operating modes). sinc4 and decimation av dd ldo dvdd ldo spi 1.25v reference temp sensor cf1 to cf4 irq0 irq1 spi pm1 pm0 ade9078 pga adc pga adc sar available in psm0 available in psm2 disabled in psm1 pga adc pga adc pga adc pga adc pga adc metrology features (per phase) irms, vrms active power, va yx, angle waveform buffer energy/power/cf accumulation line frequency etc. low power comparator 14331-034 figure 40. features available in each operating mode current channel the current channel datapath for ia, ib, and ic is shown in figure 41. the current channel adc waveforms can be sampled at the sinc4 output in the xi_sinc_dat registers at 16 ksps, or further decimated by an iir low-pass filter in the xi_lpf_dat registers at 4 ksps. gain and phase compensation are applied, creating the xi_pcf instantaneous current waveforms that update at 4 ksps. the xi_pcf waveforms are used for total active power, va r , i r m s , va , a n d f u n d a m e nt a l va r c a l c u l at i o n s . t h e x i _ p c f value is also monitored in the current peak detection circuit. the rms of the sum of instantaneous currents measurement uses the ai_pcf, bi_pcf, and ci_pcf current channel waveforms to calculate the neutral current or ro calculate the net vector current sum including the neutral current measurement, ni_pcf (see the neutral current rms, rms of sum of instantaneous currents section for more information). finally, the angle measurements indicate the time between the current channel zero crossing and the voltage channel zero crossing on the same phase or current channels on the other phases, updating at 512 ksps in the anglx_x registers. the neutral current channel, channel in, offers a neutral current sum rms and is used in an rms of instantaneous current measurement, as shown in figure 42. for more information about these calculations, see the neutral current rms, rms of sum of instantaneous currents section. channel in offers a gain calibration (nigain) and a phase calibration (nphcal). the digital integrator on channel in is enabled by setting the ininten bit in the config0 register. note that the channel in neutral current modulator is turned off in psm1.
ade9078 data sheet rev. 0 | page 28 of 107 resampled waveform data range in in analog input range phase comp integrator wf_src 0xfbff fb90 = ?67,110,000 0x0471 15c0 = +74,520,000 0x0474 e650 = +74,770,000 resampling adc_ redirect mux total active and reactive power calculation zx detection fundamental reactive power calculation total current rms va po w er calculations currentpeak detection not available in ade9078 psm1 note: acc mode.iconsel only affects ib channel calculation current channe l (ia, ib, ic) current channe l (xi_pcf) data range sinc4 + iir lpf (xi_lpf_dat) data range sinc4 output (xi_sinc_d at) data range iconsel* 0x0400 0470 = +67,110,000 zx_src_sel inten hpfdis xigainx xigain 0x46b4 = +18,100 0xb94c = ?18,100 0xfb8b 19b0 = ?74,770,000 0xfb8e ea40 = ?74,520,000 14331-035 16 ksps 4 ksps 4 ksps figure 41. current channel datapath in in analog input range phase comp integrator wf_src resampling adc_ redirect mux not available in ade9078 psm1 neutral current channel (in) inint_en nigain niphca l resampled waveform data range 0xfbff fb90 = ?67,110,000 0x0471 15c0 = +74,520,000 0x0474 e650 = +74,770,000 current channe l (xi_pcf) data range sinc4 + iir lpf (xi_lpf_dat) data range sinc4 output (xi_sinc_d at) data range 0x0400 0470 = +67,110,000 0x46b4 = +18,100 0xb94c = ?18,100 0xfb8b 19b0 = ?74,770,000 0xfb8e ea40 = ?74,520,000 14331-036 16ksps 4ksps 4ksps figure 42. neutral current channel datapath
data sheet ade9078 rev. 0 | page 29 of 107 current channel measurement update rates table 9 indicates the registers that hold current channel measurements and the rate at which they update. table 9 . current channel measurement update rates register name description update rate (ksps) ai_sinc_dat ia sinc4 f ilter o utput 16 bi_sinc_dat ib sinc4 f ilter o utput 16 ci_sinc_dat ic sinc4 f ilter o utput 16 ni_sinc_dat in sinc4 f ilter o utput 16 ai_lpf__dat ia sinc4 + iir low - pass f ilter output and decimation 4 bi_lpf__dat ib sinc4 + iir low - pass f ilter output and decimation 4 ci_lpf__dat ic sinc4 + iir low - pass f ilter o ut put and decimation 4 ni_lpf__dat in sinc4 + iir low - pass filter output and decimation 4 ai_pcf instantaneous current on ia 4 bi_pcf instantaneous current on ib 4 ci_pcf instantaneous current on ic 4 ni_pcf instantaneous current on in 4 airms filtered based total rms of ia 4 birms filtered based total rms of ib 4 cirms filtered based total rms of ic 4 nirms filtered based total rms of in 4 isumrms filtered rms of s um of i nstantaneous c urrents (ai_pcf + bi_pcf + ci_pcf ni_pcf) (see the neutral current rms, rms of sum of instantaneous currents section) 4 ipeak peak current channel sample (see the peak detection section ) 4 anglx_ x voltage to current or current to current phase angle (see the angle measurement section ) clkin/24 = 512 adc_redirect multiplexer th e ade9078 provides a multiplexer that allows any adc output to be redirected to any digital processing datapath. by default, each modulator is mapped to its corre sponding datapath. for example, the iap and ian pins go into the ia modulator, which is mapped to the ixa digital proces sing datapath. write to the adc_redirect register to change the adc to digital channel mapping. the redirection can be useful to simplify pcb layout , depending on if the ade9078 is on the top or bottom of the pcb by redirecting the ia adc output to the ic digital datapath and the ic adc ou tput to the ia digital datapath. to achie ve this configuration, write ia _din = 010 and ic_din = 000 in the adc_redirect register. alternatively , the va voltage channel output can be used for all three datapaths by writing vb_ din = 100 and vc_din = 100 in t he adc_redirect registe r . the neutral current channel does not offer a zero - crossing output or angle measurements. to calibrate the phase of the neutral current ni_pcf signal, direct the neutral current adc output to phase b digital current channel and che ck how its angle correspond s to phase a by writing ia_din = 111. reference - modul a t or v in ia_din[2:0] ai_sinc_d a t ai_lpf_d a t ia_mod 0 1 1 ib_mod ic_mod in_mod v a_mod vb_mod vc_mod ia_mod 000 001 010 100 101 1 10 11 1 14331-037 figure 43 . adc_redirect modulator to digital datapath multiplexing current channel gain, xigain there are many sources of gain error in an energy metering system. the current sensor, including current transformer burden resistors , may have some error. there is device to device gain error in the ade9078 device itself and the voltage reference may have some variation (see table 1 for the device specifications) . the ade9078 provides a current gain calibration register so that each metering device has the same current channel scaling. the current channel gain varies with xigain as shown in th e following equation: gain hpf xigain gain channel current _ 2 1 27 ? ? ? ? ? ? + = xigain = round(( current channel g ain ? 1) 2 27 ) where round() is a function to round to the nearest integer. the current channel gain can be positive or negative. for example, to increase the gain of the current channel up by 10% to 1.1, xigain = round(( 1.1 ? 1) 2 27 ) = 13,421, 773 = 0x00cc cccd to decrease the gain by 10% to 0 .9: xigain = round((0.9 ? 1) 2 27 ) = ? 13,421,773 = 0xff33 3333
ade9078 data sheet rev. 0 | page 30 of 107 it is also possible to use the c urrent c hannel g ain register to cha nge the sign of the current channel , which may be useful if the current senso r was installed backwards. to compensate for this situation, use c urrent c hannel g ain = ? 1 . xigain = round((?1 ? 1) 2 27 ) = ? 268,435, 456 = 0xf000 0000 if the m ultipoint g ain and p hase feature is used, it is recommended to use the xigain for the main correction, performed at the nominal current for the meter (see the multipoint gain and phase calibration section for more information). note that for a given phase, | current channel gain voltage channel gain power gain | 3.75 ib calculation u sing iconsel write the iconsel bit in the accmode register to calculate i b = ? i a ? i c . this setting can help save the cost of a current transformer in some 3 - wire delta configurations. see the applying the ade9078 to a 3 - wire delta service section for more information. high - pass filter a high - pass filter is provided to remove dc offsets for accurate rms and energy measurements. the ade9078 high - pass filter on the current and voltage channels is enabled by default. it can be disabled by writing the disphpf bit in the config0 register = 1 . it is recommended to leave the high - pass filter enabled to achieve the metering performance listed in t he specifications in table 1 . for some applications, it is desirable to increase the high - pass filter corner, such as to improve performance when a rogowski coil current sensor is used. the high - pass filter corner is selectable using the hpf_crn bits in the config2 register. ta ble 10 . hpf corner gain with 50 hz input si gnal hpf_ crn f ? 3 db (hz) hpf_ gain settling time to 1% for dc s tep (sec) settling time to 0.1% for dc s tep (sec) 0 38.7 0.80 0.0178 0.0268 1 19.6 0.94 0.0363 0.0544 2 9.90 0.99 0.0731 0.1097 3 4.97 1.00 0.1468 0.2202 4 2.49 1.00 0.2942 0.4412 5 1.25 1.00 0.5889 0.8833 6 (default) 0.625 1.00 1.1784 1.7675 7 0.313 1.00 2.3573 3.5359 digital integrator a digital integrator is included to allow easy interfacing to di/dt current sensors, also known as rogowski coils. the di/dt sensor output increases 20 db/decade over the freq uency range. to compensate for this increased output, the digital integrator applies ? 20 db/decade gain with a phase shift of approximately ? 9 0 . a second - order antialiasing filter is required to avoid noise aliasing back in the band of interest when the adc is sampling. to enable the digital integrator on the ia, ib , and ic channels, set the inten bit in the config0 register. to enable the digita l integrator on the neutral current, in channel, set the ininten bi t in the config0 register. figure 44 through figure 47 show the magnitude and phase response of the ade9078 digital integrator with the recommended dicoeff value of 0xffffe000. magnitude (db) frequenc y (hz) C150 0.1 1 10 100 1k C100 C50 0 50 14331-038 fig ure 44 . digital integrator magnitude response, dicoeff = 0xffffe000 phase (db) frequenc y (hz) 0 400 800 1200 1600 2000 14331-039 45 0000
data sheet ade9078 rev. 0 | page 31 of 107 magnitude (db) frequenc y (hz) 40 45 50 60 65 55 70 80 75 85 90 14331-040 figure 46 . digital integrator magnitude respo nse from 40 hz to 90 hz, dicoeff = 0xffffe000 phase (db) frequenc y (hz) 40 45 50 60 65 55 70 80 75 85 90 14331-141 47 40 90 0000 the recommended dicoeff value is 0xffffe000. phase compensation the ade9078 phase compensation uses a digital filter to achieve a phase adjustment of 0.001. this high resolution improves the total active energy and reactive energy performance at low power factors. the phase calibration range is ? 15 to +4.5 at 50 hz. to achieve this phase compensation, t he voltage channel is delayed by one 4 ksps sample, 4.5 at 50 hz. ? ? ? ? ? ? ? ? = 360 dsp line f f delay channel voltage = ? ? ? ? ? ? = 5 . 4 360 4000 50 delay channel voltage the current channel is then delayed by a digital filter according to the value rogrammed into the xphcalx register. the resulting hase correction deends on the value in the xphcalx registe r. th e following euation gives the hase correction between the inut current and voltage after the combined voltage and current delays. in the following formula hase c orrection is ositive to correct a current that lags the voltage and hase correction is negative to correct a situation where the current leads the voltage such as occurs with a current transformer ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + = cos 2 1 sin 2 C arctan C cos 2 sin C arctan (degrees) 27 C 27 C 27 C xphcalx xphcalx xphcalx correction phase where = 2 f line / f dsp . calculate t he xphcalx register value can from the desired p hase c orrection according to th e following equation: ( ) ( ) ? ? ? ? ? ? ? ? + = xphalx ? ? = 2 50/4000 = 0.07854 ( ) ( ) ( ) ( ) ( ) = = ? ? ? ? ? ? ? ? + = radians radians xphalx del a y v b y one sample 4.5 a t 50hz input vo lt age output vo lt age del a y i b y u p t o 19.5 input current current transformer sensor: current leads vo lt age output current i leads v by up to 15 phase compensation = C15 ade9078 14331-041 figure 48 . phase compensation example for current transformer, w here the current l eads the voltage ade9078 del a y v b y one sample 4.5 a t 50hz input volt age output volt age del a y i by 0 input current current lags volt age output current i lags v b y u p t o 4.5 phase correction = +4.5 14331-042 49
ade9078 data sheet rev. 0 | page 32 of 107 using the equation s in the phase compensation section , it can be seen that at 60 hz, the voltage channel delay is 5.4, as follows: = ? ? ? ? ? ? = 4 . 5 360 4000 60 (degrees) delay channel voltage this calculation leads to a hase calibration range of 15 to 5.4 at 0 hz. note that this hase comensation is euivalent to a delay or advance in time. as the line freuency varies the alied hase comensation varies as well according to the hase c orrection euation. multipoint gain and phase calibration the ade9078 allows the current chan nel gain and phase compensation to vary as a function of the calculated input current rms amplitude in xirms , which is useful to correct for the nonlinearities of current transformer sensors to achieve very high meter accuracy, for example in class 0.2 met ers. multipoint gain and phase the current channel gain, xigain, is applied regardless of the xirms input signal level. this gain compensate s for the nominal gain error of the current channel, including the current transformer and burden resistors. if mult i point gain and phase compensation is enabled, an additional current gain value is applied based on the xirms value to compensate for the current transformer gain shift over input signal amplitude. the current channel datapath is shown in figure 51. if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, an additional gain factor, xigain0 through xi gain4 , is applied based on the xirms current rms amp litude and the mtthr_lx and mtthr_hx register values, as shown in figure 50. the applied current channel phase compensation varies based on the xirms i nput signal level as well if multipoint gain and phase compensation is enabled. gain, phase correction mtthr_l1 , mtthr_h0 mtthr_h4 = full scale mtthr_l0 = 0 region0 region1 region2 region3 region4 mtthr_l2 , mtthr_h1 mtthr_l3 , mtthr_h2 mtthr_l4 , mtthr_h3 xigain4 xphcal4 xigain3 xphcal3 xigain2 xphcal2 xigain1 xphcal1 xigain0 xphcal0 x x x x x 14331-043 figure 50 . multipoint gain and phase calibration the mtthr_lx and mtthr_hx registers set up the regions in which to apply each set of corrections, al lowing hysteresis. the decision of which coefficients to apply is done according to the following rules: if xirms >mtthr_h[current_region] if current_region 3 current_region++; else if xirms < mtthr_l[current_region] if current_region 1 current_region--; xigain = xigain[current_region]; xphcal = xphcal[current_region]; xmtregion = current_region; for example, if airms goes above mtthr_h2, the gain and phase correction is set to aigain3 and aphcal3, respectively. then, if airms goes below mtthr_l3, the gain and phase correction is set to aigain2 and aphcal2. for proper operation, the value of the registers must be increasing such that mtthr_l0 < mtthr_l1 < mtthr_h0 < mtthr_l2 < mtthr_h1 < mtthr_l3 < mtthr_h2 < mtthr_l4 < mtthr_h3 < mtthr_h4 . the following example configuration us es two regions, such that region 0 is used from 0 a to 20a and region 1 is used from 22 a to f ull s cale: ? mtthr_l0 = 0 ? mtthr_l1 = 0x95 9ac1 (20 a for this meter) ? mtthr_h0 = 0xa4 90a 2 (22 a for this meter) ? mtthr_l2 = 0x7fffffffe (maximum positive threshold ? 1) ? mtthr_h1 = 0x7ffffffff (maximum positive threshold) the xmtregion registers indicate the current region for each phase and correspondingly, which xigainx and xphcalx coefficients are being applied. m ultipoi nt phase and gain calibr ation is disabled by default. to enable it, set the mten bit in the config0 register. single - point gain and phase when multipoint gain and phase calibration is disabled, single - point gain and phase calibration is allowed. i n this case, the xigain register is applied. no additional curren t channel gain is applied based on the xirms amplitude. when multipoint gain and phase calibration is disabled, the xphcal0 phase compensation is always applied regardless of the xirms value.
data sheet ade9078 rev. 0 | page 33 of 107 hpf in in +1v analog input range 0v ?1v ade9078 phase comp current rms (xirms) integrator ib = ?ia?ic adc_ redirect mux total active and reactive power calculation fundamental reactive power calculation current peak detection total va power calculation not available in ade9078 psm1 note: acc mode.iconsel only affects ib channel calculation current channel (ia, ib, ic) iconsel* inten hpfdis xigainx xigain mten if mten = 1, xigainx, phase comp changes based on xirms, mtthr_lx and mtthr_hx 0: xigainx = xigain0; phase comp = xphcal0 1: xigainx = xigain1; phase comp = xphcal1 2: xigainx = xigain2; phase comp = xphcal2 3: xigainx = xigain3; phase comp = xphcal3 4: xigainx = xigain4; phase comp = xphcal4 xirms xi_pcf 0xfbff fb90 = ?67,110,000 sinc4 output (xi_sinc_dat) data range 0x0400 0470 = +67,110,000 0x0471 15c0 = +74,520,000 sinc4 + iir lpf (xi_lpf_dat) data range 0xfb8e ea40 = ?74,520,000 0x0474 e650 = +74,770,000 current channe l (xi_pcf) data range 0xfb8b 19b0 = ?74,770,000 14331-044 figure 51. current channel with multi-point gain and phase correction 14331-085 xvgain hpf voltage peak detection reference - ? modulator vp v in v in +1v analog input range 0v ?1v vn ade9078 voltage channel sinc4 lpf 4:1 wf_src wf_cap_sel hpfdis xv_pcf adc_ redirect mux total active and reactive power calculation zx_src_sel zx detection total voltage rms va power calculations fundamental reactive power calculations note: consel supports several 3-wire and 4-wire hardware configurations 100 va = va ? vb; vb = va ? vc; vc = vc ? vb; vb = ?va vb = ?va ? vc vb = va ? vc 011 010 001 000 resampled waveform data range 0v 0v 0v 0xfbff_fb90 = ?67,110,000 0x0471_15c0 = +74,520,000 0x0474_e650 = +74,770,000 0v voltage channe l (xv_pcf) data range sinc4 + iir lpf (xv_lpf_dat) data range sinc4 output (xv_sinc_dat) data range 0x0400_0470 = +67,110,000 0x46b4 = +18,100 0xb94c = ?18,100 0xfb8b_19b0 = ?74,770,000 0xfb8e_ea40 = ?74,520,000 16 ksps 4 ksps waveform buffer resampling vconsel* 4 ksps not available in ade9078 psm1 figure 52. voltage channel datapath
ade9078 data sheet rev. 0 | page 34 of 107 table 11. voltage channel measurement update rates register name description update rate av_sinc_dat va sinc4 f ilter o utput 16 ksps bv_sinc_dat vb sinc4 f ilter o utput 16 ksps cv_sinc_dat vc sinc4 f ilter o utput 16 ksps av_lpf_ dat va sinc4 + iir low - pass filter and decimator output f dsp = 4 ksps bv_lpf_dat vb sinc4 + iir low - pass filter and decimator output f dsp = 4 ksps cv_lpf_dat vc sinc4 + iir low - pass filter and decimator output f dsp = 4 ksps av_pcf instantaneous voltage on va f dsp = 4 ksps bv_pcf instant aneous voltage on vb f dsp = 4 ksps cv_pcf instantaneous voltage on vc f dsp = 4 ksps avrms filtered based t otal rms of va f dsp = 4 ksps bvrms filtered based t otal rms of vb f dsp = 4 ksps cvrms filtered based t otal rms of vc f dsp = 4 ksps vpeak peak current channel sample (see the peak detection section ) f dsp = 4 ksps aperiod line period measurement on va f dsp = 4 ksps bperiod line period measur ement on vb f dsp = 4 ksps cperiod line period measurement on vb f dsp = 4 ksps com_period line period measurement on combined signal from va, vb, vc (see the combined voltage zero crossing section ) f dsp = 4 ksps anglx_x voltage to current or current to current phase angle (see the angle measurement section ) clkin/24 = 512 ksps voltage channel the voltage channel datapath is shown in figure 52. the voltage channel adc waveforms can be sampled at the sinc4 output, in the xv_sinc_dat registers, at 16 ksps or further decimated by an iir low - pass filter, in xv_lpf_dat registers at f dsp = 4 ksps . gain and phase compensation are applied, creating the xv_pcf instantaneous voltage waveforms that update at f dsp = 4 ksps . the xv_pcf waveforms are used for t otal active power , va r , i r m s , va , and f undamental var calculations. the xv_pcf value is also mon itored in the voltage peak detection circuit. finally, angle measurements indicate the time between the voltage channel zero crossing and the current channel zero crossing on the same phase or voltage channels on the other phases, updating at clkin/24 = 51 2 ksps in the anglx_x registers. the line period measurement xperiod indicates the line p eriod , as described in the line period calculation section. vo ltage channel measurements table 11 indicates the registers that hold voltage channel measurements and the rate at which they update. voltage channel gain use t he xvgain registers to calibrate the voltage channel of each phase. the xvgain register has the same scaling as the xigain register. gain hpf xigain gain channel voltage _ 2 1 27 ? ? ? ? ? ? + = current channel gain voltage channel gain power gain | 3.75 energy measurements overview figure 53 shows how ai_pcf and av_pcf calculat e per phase rms and power and how the calculated rms and power are accumulate d into the awatthr and awatt_acc registers and the cfx pulse outputs. per phase energy measurements update rate instantaneous power measurements, including as xwatt, xvar, xva, xfvar, update at a rate of f dsp = 4 ksps . these measurements are accumulated into power measurements in xwatt_acc register that update at a user defined interval ranging from 500 s to 2 s ec , depending on the selection in the pwr_time register. energy measurements update every 4 ksps by default and can store up to 211 s ec of accumulation at full scale. alternatively, these registers can be set into a different accumulation mode where they update after a user defined number of line cycles or samples. the power factor measurements update every 4096/4 ksps = 1.024 s ec.
data sheet ade9078 rev. 0 | page 35 of 107 ai_pcf av _pcf per phase rms and power calculation awatthr avarhr afvarhr avahr per phase energy accumulation awatt_acc avar_acc afvar_acc ava_acc cf1 pulse output cf2 pulse output cf3 pulse output cf4 pulse output energy to frequency awatt avar afvar airms av rm s ava ade9078 per phase power accumulation 14331-045 figure 53. per phase power and energy calculations from xi_pcf and xv_pcf waveforms table 12. active power related register update rate register name description update rate awatt low-pass filtered total active power on phase a 4 ksps bwatt low-pass filtered total active power on phase b 4 ksps cwatt low-pass filtered total active power on phase c 4 ksps awatt_acc accumulated total active power on phase a after the pwr_time 4 ksps samples, from 500 s to 2.048 sec bwatt_acc accumulated total active power on phase b after the pwr_time 4 ksps samples, from 500 s to 2.048 sec cwatt_acc accumulated total active power on phase c after the pwr_time 4 ksps samples, from 500 s to 2.048 sec awatthr accumulated total active energy on phase a according to the settings in ep_cfg and ep_time; holds up to 211 sec of energy at full scale bwatthr accumulated total active energy on phase b according to the settings in ep_cfg and ep_time; holds up to 211 sec of energy at full scale cwatthr accumulated total active energy on phase c according to the settings in ep_cfg and ep_time; holds up to 211 sec of energy at full scale apf phase a power factor (see the power factor section) every 1.024 sec bpf phase a power factor (see the power factor section) every 1.024 sec cpf phase a power factor (see the power factor section) every 1.024 sec
ade9078 data sheet rev. 0 | page 36 of 107 power-based and filter-based rms measurement algorithms filter-based total rms the ade9078 offers current and voltage rms measurements, which are calculated by squaring the input signal, low-pass filtering, and then taking the square root of the result, as shown in figure 54. x 2 2 15 xrmsos xrms 52,866,837 xv_pcf or xi_pcf voltage or current channel waveform 14331-046 figure 54. filter based rms the low-pass filter, lpf2, extracts the rms value, attenuating harmonics of a 50 hz or 60 hz fundamental by at least 64 db so that at full scale, the variation in the calculated rms value is very small, 0.064% error. note that the rms reading variation increases as the input signal becomes smaller because the noise in the measurement increases. the filter based rms measurement is typically within 0.5% error over a 5000:1 dynamic range and within 0.1% error over a 1000:1 dynamic range. refer to the specifications in table 1 to understand what performance to expect from this measurement. note that the xrms register does not read 0 with the xp and xn inputs shorted together. the filter based rms has a bandwidth of 1.6 khz, as given in table 1. the rms calculations, one for each channel, airms, birms, cirms, nirms, avrms, bvrms, and cvrms, are updated every 4 ksps. the isumrms calculation uses the same method to calculate isumrms, where i sum = i a + i b + i c i n , and also updates at 4 ksps (see the neutral current rms, rms of sum of instantaneous currents section for more information). the xrms value at full scale is 52,866,837d. table 13 shows the rms settling time to 99% of full scale for a 50 hz signal. table 13. rms settling time configuration rms settling time, fs = 99% (sec) integrator on, hpf on, and lpf2 on 1.09 integrator off, hpf on, and lpf2 on 0.96 for high performance at small input signals, below 1000:1, it is recommended to calibrate the offset of this measurement using the xrmsos registers. the offset must be calibrated at the smallest input signal that requires good performancedo not calibrate this measurement with zero input signal. the following equation indicates how the xrmsos register value modifies the result in the xrms register: xrmsos xrms0 xrms ?? ? 152 2 where xrms0 is the initial xrms register value before offset calibration. at 1000:1, the expected xrms0 = 52,866,837/1000 = 52,866.837. then, one bit in the xrmsos register changes xrms by (52,867.147 ? 52,866.837)/52,866.837 = 0.0006%. 147.867,5212 1000 52,866,837 15 2 ??? ? ? ? ? ? ? ? xrms neutral current rms, rms of sum of instantaneous currents the ade9078 calculates the neutral current rms from a neutral current sensor input into the inp and inn pins, and stores the result in the nirms register. a nirmsos register allows offset calibration of this measurement. the scaling is the same as for the other xirms and xirmsos registers (see the filter-based total rms section for more information). the ade9078 also calculates the rms of i sum = i a + i b + i c i n and stores the result in isumrms. an isumrmsos register allows offset calibration of this measurement. the scaling is the same as for the other xirms and xirmsos registers (see the filter-based total rms section for more information). if a neutral current sensor is not used, write 0 to the isum_cfg bits in the config0 register, and then isumrms approximates the neutral current from the sum of ia, ib, and ic. if the measured neutral current, ni_pcf, deviates from the sum of ai_pcf + bi_pcf + ci_pcf current channel waveforms, there may be a fault in the system. to determine how big the mismatch is between the measured neutral current and the measured channel a, channel b, and channel c currents, select isum_cfg[1:0] to 01 or 10 based on the direction of the neutral current with respect to the other current channel waveforms. table 14. i sum configuration options isum_cfg[1:0] i sum calculation 00, 11 i sum = ai_pcf + bi_pcf + ci_pcf 01 i sum = ai_pcf + bi_pcf + ci_pcf + ni_pcf 10 i sum = ai_pcf + bi_pcf + ci_pcf ? ni_pcf isumrms has the same scaling as xirms. note that if ai_pcf, bi_pcf, and ci_pcf are all at full scale and in phase with each other, with isum_cfg = 00 or 11, isumrms is 3 52,866,837d = 158,600,511d. if ai_pcf, bi_pcf, ci_pcf, and ni_pcf are all
data sheet ade9078 rev. 0 | page 37 of 107 at full scale and in phase with each other, with the isum_cfg = 01 then isumrms is 4 52,866,837 d = 211,467,348d. to receive an indic ation if isumrms exceeds a threshold, configure isumlvl. the mismtch bit in status0 and associated interrupt indicate if there is a change in the relationship between isumrms and isumlvl. cal c ulate the desire d value of isumlvl according to th e following eq uation: ? ? ? ? ? ? = x scale full xirms isumlvl _ _ where : xirms_full_scale is the nominal xirms value with full - scale inputs, 52,866,837 . x is the desired current level to indicate a mismtch error. for example, set the isumlvl to warn about a rms of sum of instantaneous currents greater than 10,000:1 from full scale, x = 10,000. total active power total active power is commonly use d for billi ng p urposes. it includes power on the fundamental and on the harmonics. figure 55 shows how the low - pass filtered total active power on phase a is calc ulated. first, the ai_pcf and av_pcf waveforms are multiplied together. then , the result is low - pass filtered, unless disaplpf = 1. finally, the apgain is applied to perf orm a gain correction and the awattos value is applied to correct the active power off set. apgain aw a t t os aw a tt lpf2 disaplpf ai_pcf av_pcf energy/ power/ cf accumul a tion 14331-047 figure 55 . total active power ( awatt ) c alculation figure 56 shows the relationship between the i and v input signals and the instantaneous active power and low - pass filtered active power, assuming that i and v are at full scale with just the fundamental present and a power factor of 1. if disaplpf = 1, awat t r e f l ect s the i nstantaneous a ctive p ower and if it is 0, awatt reflects the low - p ass f iltered a ctive p ower in figure 56 , assuming that apgain = 0 and awat t os = 0. C0.062% +0.062% lo w -p ass fi l tered active power 20,823,646 0 instantaneous active power i, v fundamen t a l input signa l 14331-048 figure 56 . instantaneous active power and low - pass filtered active power at a power factor of 1 the low - pass filter, lpf2, e xtracts the total active power, attenuating harmonics of a 50 hz or 60 hz fundamental by 64 db so that at full scale, the variation in the low - pass filtered active power is very small, 0.062% . the resulting awatt signal has an update rate of 4 ksps and a bandwidth of 1.6 khz , as given in table 1 . phase b and phase c have similar datapaths to those described for awatt to calculate bwatt and cwatt, with individual gain and phase coefficients, bpgain and bwattos, and cpgain , and cwattos . the xpgain register has the same scaling as the xigain register ( see the equation s in the current channel gain, xigain section) . note that for a given phase, | curr ent channel gain voltage channel gain power gain | 3.75 xwattos has the same scaling as xwatt. to understand how x wat t o s a ffects the xwatt value, use the following e quation : ? ? ? ? ? ? ? ? ? ? ? ? = x scale full xwatt xwattos _ _ 1 where : xwatt_full_scale is the nominal xwatt value with full - scale inputs, 20,823,646 . note that xvar and va have the same scaling , so the same equation can be used for all three offsets. x is the smallest power level to calibrate. for example, to calibrate the energy at 10,000 from full scale, x = 10,000. % 05 . 0 000 , 10 20,823,646 1 = ? ? ? ? ? ? ? ? ? ? ? ? = xwattos
ade9078 data sheet rev. 0 | page 38 of 107 then, each bit in the xwattos register can correct an error of 0.05% at 10,000:1. note that in most applications, the total active power performance with small inputs is sufficient with xwattos at zero. table 15 shows the settling times for total active power for a 50 hz signal. table 15. total active power settling time total active power settling time (sec) configuration fs = 99% fs = 99.90% integrator on, hpf on, and lpf2 on 0.85 1.2 integrator off, hpf on, and lpf2 on 0.85 1.2 integrator off, hpf on, and lpf2 off 0.06 0.66 tot a l re a c ti ve power total reactive power includes reactive power on the fundamental and on the harmonics. the current channel, ai_pcf, is shifted by 90 at the fundamental and at all harmonics. then, this signal is multiplied by the voltage waveform, av_pcf. then the result is low-pass filtered, unless disrplpf = 1. finally the apgain is applied to perform a gain correction and the avaros value is applied to correct the var offset. note that, in most applications, the total reactive power performance with small inputs is sufficient with avaros at zero. figure 57 shows how the total reactive power calculation is performed. apgain avaros avar lpf2 disrplpf ai_pcf av_pcf energy/ power/ cf accumulation 90 degree phase shift 2 14331-049 figure 57. total reactive power (avar) calculation the total reactive power at a power factor of 0 has a similar ripple to the total active power at a power factor of 1 (see figure 56). the resulting avar signal has an update rate of 4 ksps and a bandwidth of 1.6 khz, as given in table 1. phase b and phase c have similar datapaths to those described for avar to calculate bvar and cvar, with individual gain and phase coefficients, bpgain and bvaros, and cpgain and cvaros. xvaros has the same scaling as xvar (see the total active power section to understand how to calculate this register value). it is possible to disable total reactive power by setting the var_dis register. note that the run register must be set to 0 before changing the var_dis setting and must then be set to 1 again. table 16 shows the settling times for total reactive power for a 50 hz signal. table 16. total reactive power settling time total reactive power settling time (sec) configuration fs = 99% fs = 99.90% integrator on, hpf on, and lpf2 on 0.85 1.19 integrator off, hpf on, and lpf2 on 0.85 1.19 integrator off, hpf on, and lpf2 off 0.02 0.07 tot a l app arent power apparent power is generated by multiplying the current rms measurement, xirms by the corresponding voltage rms, xvrms and then applying a gain correction, apgain. the result is stored in the ava register. note that the offset of the total apparent power calculation is performed by calibrating the airms and avrms measurements, using the airmsos and avrmsos registers (see the filter-based total rms section for more information on the rms calculation). the resulting ava signal has an update rate of 4 ksps and a bandwidth of 1.6 khz, as given in table 1. phase b and phase c have similar datapaths to those described for ava to calculate bva and cva, with individual gain coefficients, bpgain and cpgain. in some applications, if a tamper is detected on the voltage channel inputs, it is desirable to accumulate the apparent energy assuming that the voltage were at a nominal level. the ade9078 offers a register (vnom) that can be set to a value to correspond to 240 v rms. if the vnomx_en bits in the config0 register are set, vnom is multiplied by xirms when calculating xva. table 17 shows the settling times for total apparent power for a 50 hz signal. table 17. total apparent power settling time configuration total apparent power settling time, fs = 99% (sec) integrator on, hpf on, and lpf2 on 1.09 integrator off, hpf on, and lpf2 off 0.96 airmsos apgain airmsos airms ava avrms vnom lpf2 ai_pcf x 2 2 15 2 15 lpf2 ai_pcf energy/ power/ cf accumulation 1 x 2 0 14331-050 figure 58. total apparent power (ava) calculation
data sheet ade9078 rev. 0 | page 39 of 107 fundamental reactive power the fundamental reactive power in the ade9078 is calculated using a proprietary algorithm that requires initialization of the network frequency and of the nominal voltage measured in the voltage channel. the selfreq bit in the accmode register s elects whether the system is 50 hz or 60 hz. for a 50 hz system , clear the selfreq bit , and for a 60 hz system, set the selfreq bit t o 1. the sel freq selection must be made prior to writing 1 to the run regis ter. the vlevel register indicates the nominal value of the voltage channel. calculate vlevel according to the following equation: vlevel = x 1,144,084 w here x is the d ynamic r ange that the nominal input signal is at with respect to full scale. it is recommended to set the voltage channel input so that the nominal voltage, for example 240 v rms, corresponds to one hal f of the analog input signal range of the ade9078 . the ade9078 can support 1 v peak, 0.707 v rms inputs, so i t is recommende d to scale the voltage channel inputs to 0.353 v rms. then, with a nominal input of 240 v, the input signal is at half of full scale and x is equal to 2. write 2,288,168d to the vlevel register to configur e this feature . v level = 2 1,144,0 84 = 2,288,168 after configuring the selfreq and vlevel parameters , the ade9078 tracks the fundamental line frequency within 5 hz of the 50 hz or 60 hz frequency selected in selfreq. if a larger frequency range than 5 hz is required in the application, monito r the line period ( xperiod ) and change the selfreq selection accordingly. note that the run register must be set to 0 before changing the selfreq setting and must then be set to 1 agai n. the fundamental current signal is shifted by 9 0 and multiplied by the fundamental voltage signal. this is then gained by apgain and offset correction is applied according to the afvaros register. apgain af v aros af v ar ai_pcf a v_pcf fundamen t a l v ar energy/ power/cf accumul a tion 14331-051 figure 59 . fundamental reacti ve power, afvar the fundamental reactive power at a power factor of 0 has a similar ripple to the total active power at a power factor of 1 (see figure 56 ). xfvaros has the same scaling as xfvar (see the tota l ac t ive power section to understand how to calculate this register value. table 18 shows the settling times for fundamental reactive power for a 50 hz signal. table 18. fundamental reactive p ower s ettling t i me fundamental rea ctive power settling t ime (sec) configuration fs = 99% fs = 99.90% integrator on, hpf on, and lpf2 on 0.8 6 1.1 1 integrator off, hpf on, and lpf2 on 0.8 6 1.1 1 power factor the total active power and total apparent power are accumulated over 1.024 s ec . then the power factor is calculated on each phase according to th e following equation: sec 1.024 over d accumulate ava sec 1.024 over d accumulate awatt apf = capacitive: current leads voltage inductive: current lags voltage watt 90 lagging inductive: current lags voltage capacitive: current leads voltage w a tt (C) v ar (+) quadrant ii w a tt (+) v ar (+) quadrant i w a tt (C) v ar (C) quadrant iii w a tt (+) v ar (C) quadrant iv w a tt(+) indic a tes power received (imported from grid) w a tt(C) indic a tes power delivered (exported t o grid) 2 = 60 pf 2 = 0.5 ind 1 = C30 pf 1 = 0.866 ca p 14331-052 figure 60 . active power and var sign for capacitive and inductive loads the power factor results is stored in 5.27 format. the highest power factor value is 0x07ff ffff, which corresponds to a pow er factor of 1. a power factor of ? 1 is stor ed as 0xf800 0000. to determine the power factor from the xpf register value, use th e following equation: power factor = apf 2 ?27
ade9078 data sheet rev. 0 | page 40 of 107 energy accumulation figure 61 shows how awatt is accumulated into the awatthr and awatt_acc registers. a no load threshold is applied and the energy sign is checked to determine whether to accumulate the awatt sample into the internal energy accumulator. the internal energy accumulator is either added to the awatthr register or latched depending on the egy_ld_accum setting at a egyrdy rate (see the reloading or accumulating user energy register section for more details). the awatt value is directly accumulated into the internal power accumulator and latched into awatt_acc at a pwrrdy rate. set the egy_pwr_en bit in ep_cfg register to run the energy and power accumulator. signed energy accumulation modes total active energy accumulation modes in some installations, it is desirable to bill for only positive total active energy. the ade9078 offers a way to do so using the wattacc bits in the accmode register. to set the total active energy accumulation and any corresponding cf pulse output for positive energy only, write 10 to wattacc. if wattacc = 0, the energy accumulation is signed. the msb of the awatthr_hi register indicates whether the energy is negative or positive. other accumulation modes include absolute accumulation mode with wattacc = 01, where the absolute value of awatt is accumulated, and negative only accumulation mode with wattacc = 11, where only negative active energy is accumulated. reactive energy accumulation modes in some installations, because reactive energy may change frequently between positive and negative values with inductive and capacitive loads, it is desirable to bill for the absolute value of reactive energy. the ade9078 offers a way to do so using the varacc bits in the accmode register. to set the total and fundamental reactive energy register and any corresponding cf pulse output to accumulate the absolute value of reactive energy, write 01 to varacc. no load check 0 internal energy accumulator 41 31 digital to frequency converter 4.096mhz awatt wattacc[1:0] act_nl_lvl + + 0 check sign to determine whether to accumul ate 0 anoload ep_cfg. noload_tmr 1 wthr cf1den cf_lcfg cfmode revpsumx cfx power energy low-pass filtered total active power internal power accumulator f dsp egyrdy 31 0 031 awatthr_hi 19 0 0 1 egy_ld_accum internal energy accumulator value added to awatthr or latched into awatthr at egyrdy rate pwrrdy internal power accumul ator value latched in to awatt_acc when pwr_timer samples have been accumul ated f dsp 14331-053 awatthr_lo figure 61. awatt accumulation into energy and power, using no load threshold and signed accumulation mode
data sheet ade9078 rev. 0 | page 41 of 107 i f va r a c c = 0, the total and fundamental reactive energy accumulation is signed. the msb of the avarhr_h i register indicates whether the energy is negative or positive. other accumulation modes offered include positive only accumulation mode with varacc = 10, and negative only accumulation mode where only negative reactive energy is accumulated with varacc = 11. no load detection no load detection prevents energy accumulation due to noise, when the input currents are below a given meter start current. to determine if a no load condition is present, the ade9078 evaluates if the accumulated energy is below a user defined threshold over a user defined time period. this no load detection is done on a per phase and per energy basis. the noload_tmr bits in the ep_cfg register determine whether to evalua te the no load condition over 64 samples to 4096 samples ( 64/ 4 ksps = 16 ms to 1.024 s ec) by writing to the noload_tmr bits as described in table 19 . no load detection is enabled by default, over the minimum time of 64/4 ksps = 16 ms. no load detection is disabled when the noload_tmr[2:0] bits in the ep_cfg register = 111b. table 19. no load condition evaluation time noload_tmr samples to evaluate in no load condition time t hat no load detection i s evaluated (ms) 0 64 16 1 128 32 2 256 64 3 512 128 4 1024 256 5 2048 512 6 4096 1024 7 no load disabled no load disabled the user defined no load thresholds are written into the act_nl_lvl, react_nl_lvl, and app_nl_lvl registers. the act_nl_lvl register sets the no load threshold for the total active energy. correspondingly the react_nl_lvl register sets the no load threshold for total and fundamental reactive energy wh ereas the app_nl_lvl sets the no load threshold for total apparent energy. the no load thresholds are calculated according to th e following equation: ? ? ? ? ? ? = x scale full xwatt lvl xnl 64 _ _ _ where : xwatt_full_scale is th e nominal xwatt value with full - scale inputs, 20,823,646 . note that xvar and va have the same scaling so the same value can be used for all three thresholds. x is the desired no load input power level. for example, to set the no load threshold to zero out energy below 50,000 from full scale, x = 50,000 . th us , for a 50,000:1 no load threshold level, xnl_lvl i s 0x6804 . e 1 68 x 0 654 , 26 000 , 50 64 20,823,646 _ = = ? ? ? ? ? ? ? ? = lvl xnl when a hase is in no load every f dsp = 4 sps zero energy is accumulated into the energy registers and cf accum ulation. note that the x_acc registers are not affected by no load detection. even when in no load any ower calculated in the resective xwatt xvar and xva register s is accumulated into the corresonding x_acc register every f dsp = 4 sps . no load indications the phnoload register indicates whether each phase of energy is in no load . f or example, bit 2 through bit 0 in the phnoload register indicate whether phase a total apparent energy, reactive energy , and act ive energy are in phase on bit 2 throu gh bit 0, respectively. if a bit is set, it indicates that the phase energy is in no load if it i s clear, the phase is not in no load . the user can enable an interrupt to occur when the no load status of one of the per phase energy changes, either going in to or out of no load . there is an interrupt enable bit for each type of energy. set the rfnoload, vanload, rnload, and anload bits in the status1 register to enable an interrupt on irq1 when one or more phases of f undamental var, t otal va , t o t a l va r , and t otal active power no load changes status. there is also an option to indicate the no load status on the event pin (see the interrupts/e vents section for more information ) . figure 62 shows what happens when the xwatt, low - pass filtered active power value goes above the user configured , no load threshold and then back down below it again. the same concept applies to all of the energy values (total and fundamental var, total va) wi th the corresponding react_nl_lv l and app_nl_lvl no load thresholds. lo w -p ass fi l tered active power (x w a tt) active energ y no load threshold (act_nl_ l vl) no load accumul a tion inte r v al is set in noload_tmr active energ y no load accumul a t or no load indic a tion anoload) active energ y , xw a tthr 14331-054 figure 62 . no load detection and indication
ade9078 data sheet rev. 0 | page 42 of 107 energy accumulation details internal energy register over flow rate there are 42 - bit internal signed energy accumulators for each phase of each energy accumulation, as shown in figure 61 . these accumulators u pdate at a rate of f dsp = 4 ksps . to calculate the time until the internal accumulator overflows with full - scale inputs and all digital gain and offset factors at zero, use the following equation . maximum internal energy accumulator time (sec) = ? ? ? ? ? ? ? ? dsp f scale full at awatt _ _ _ 2 41 where awatt_at_full_scale refers to the nominal awatt value with full - scale input s. for example , with mten = 0 , for single - point gain compensatio n and aigain, avgain, apgain, and awatto s all equal to zero, the phase a total active ene rgy has a digital gain of 1. th us, the phase a total active energy accumulated in the internal accumulator overflows in 26.4 sec with the nominal full - scale awatt value of 20,823,646 . maximum internal energy accumulator time (sec) = sec 4 . 26 4000 20,823,646 2 41 = ? ? ? ? ? ? ? ? user energy register update rate, egyrdy as shown in figure 61 , the internal energy accumulator is latched into a user accessible energy register or a dded to a user accessible register at a rate of egyrdy. figure 63 further sho w s how the egyrdy update rate is generated. the egyrdy update rate occurs after egy_time + 1 f dsp samples or egy_time + 1 half line cycles, according to the egy_tmr_ mode bit in the ep_cfg register. if egy_tmr_mode = 0 , select the sample - based accumulation as follows : internal energy accumulator time (sec) = ? ? ? ? ? ? ? ? + dsp f time egy 1 _ the egy_time[12:0] register allows up to (8191 + 1) = 8192 samples to be accumulated, which corresponds to 8192/4000 = 2.048 sec if egy_tmr_mode = 0 . internal energy accumulator time (sec) = sec 048 . 2 4000 1 8191 = ? ? ? ? ? ? + internal energy accumulator time (sec) = ? ? ? ? ? ? ? ? + rate zx time egy _ 1 _ with a 50 hz line frequency and a zero - crossing interrupt rate of 100 hz, the maximum accumulation time is 81.92 sec with egy_time equal to 0x1fff (81 91d). internal energy accumulator time (sec) = 92 . 81 100 1 8191 = ? ? ? ? ? ? + energ y power 0 zx_se l 1 1 1 1 0 zx v a zxvb zxvc zxcomb 0 0 0 1 cf3_cfg c f 3 0 1 egy_tmr_mode cf3/zxpin counter egy_time[12:0] + 1 e q u a l ? egyrd y upd a ter a te egyrd y counter pwr_time[12:0] + 1 equal? pwrrd y upd a te r a te pwrrd y f ds p f ds p 14331-055 figure 63 . egyrdy and pwrrdy update rates reloading or accumulating user energy register when an egyrdy event happens, the internal energy accumulation is either directly loaded into the xwatthr register or added to the existing accumulati on based on the state of the egy_ld_accum bit in the ep_cfg register. if egy_ld_accum = 0, the internal energy register is added to the user accessible energy register. if egy_ld_accum = 1, the internal energy register overwrites the user accessible energ y register. finally, the internal energy accumulator reset s and starts counting again from zero. user energy register overflow rate there are 45 - bit user accessible signed energy accumulators for each phase of each energy accumulation. these accumulators u pdate at a rate according to egyrdy, as described in the user energy register update rate, egyrdy section. the following equation shows how to calculat e the time until the user accessible accumulator overflows with full - scale inputs and all digital gain and offset factors at zero . for this example, assume that the energy register is updating at every f dsp = 4 ksps sample. maximum user energy accumulator time (sec) = ? ? ? ? ? ? ? ? dsp f scale full at awatt _ _ _ 2 44 where awatt_at_full_scale refers to the nominal awatt value with full - scale inputs .
data sheet ade9078 rev. 0 | page 43 of 107 for example, with mten = 0, for single-point gain compensation and aigain, avgain, apgain, and awattos all = 0, the phase a total active energy has a digital gain of 1. then, the phase a total active energy, accumulated in the user accessible accumulator, overflows in 211 sec with the nominal full-scale awatt value of 20,823,646. maximum user energy accumulator time (sec) = sec211 4000 20,823,646 2 44 ? ? ? ? ? ? ? ? ? ? accessing the user energy registers each 45-bit user accessible signed energy accumulator is divided into two registers: a register containing the 32 msbs, xhr_hi, and a register containing the 13 lsbs, xhr_lo, as shown in figure 64. f dsp 0 internal energy accumulator 41 31 + + 31 0 031 awatthr_hi 19 awatt awatthr_lo 14331-056 figure 64. internal energy register to awatthr_hi and awatthr_lo the expected user energy accumulation can be calculated according to the following formula based on the average awat t va lue: user energy accumulation = awatt ( egy_time + 1) then, awatthr_hi contains 32 msbs, which can be calculated by rounding the following equation down to the nearest whole number: awatthr_hi = rounddown( user energy accumulation 2 ?13 ) where rounddown() is a function to round down to the nearest integer. finally, awatthr_lo is calculated based on the two previous values, as follows: awatthr_lo = ( user energy accumulation ? awatt_egy_user_hi 2 13 ) 2 19 for example, if 4000 samples of awatt are accumulated, with full-scale inputs, the expected value of awatthr_hi is 0x009b 25f4 and awatthr_lo is 0xe600 0000. user energy accumulation = 20,823,646 (3999 + 1) = 83,294,584,000 awatthr_hi = rounddown (83,294,584,000 2 ?13 ) = 10,167,795 = 0x009b 25f3 awatthr_lo = (83,294,584,000 ? 10,167,795 2 13 ) 2 19 = 3,858,759,680 = 0xe600 0000 to determine the consumption in watthours, the meter is calibrated using the xigain, xvgain, and xpgain registers. then, xwatthr_hi watthour/lsb = watthour. the watthour/lsb constant is the same for all meters. read user energy register with reset if the rd_rst_en bit is set in the ep_cfg register, when a user accessible energy register is read, its contents are reset. for example, if awatthr_hi is read, the awatthr_hi register value goes to zero. the awatthr_lo register contents are not modified. it is not recommended to read the xhr_lo registers with reset. user energy register use models there are three main use models for energy accumulation, as follows: ? read the energy register with reset ? accumulate energy over a defined number of line cycles ? accumulate energy over a defined number of samples to read the energy register with reset, use the following settings: ? set the configuration register as follows: ? egy_ld_accum = 0 ? egy_tmr_mode = 0 ? rd_rst_en = 1 ? egy_pwr_en = 1 ? egy_time = 1 ? for the output, read only the xhr_hi register, which has enough resolution for most applications. the xhr_lo register is maintained and accumulated and does not need to be read by the user. ? set the maximum time before reading xhr_hi to prevent overflow with full-scale inputs to 211 sec. to accumulate energy over a defined number of line cycles, use the following settings: ? set the configuration register as follows: ? egy_ld_accum = 1 ? egy_tmr_mode = 1 ? rd_rst_en = 0 ? egy_pwr_en = 1 ? egy_time to the desired number of half line cycles ? for the output, the xhr_hi register has enough resolution for most applications. to maintain perfect synchronization with the cf pulse output, the xhr_lo must be read as well because it is cleared at every egyrdy cycle. ? set the maximum time before reading xhr_hi to prevent overflow with full-scale inputs to 26.4 sec.
ade9078 data sheet rev. 0 | page 44 of 107 to accumulate energy over a defined number of samples , use the following settings: ? set the c onfiguration r egister as follows: ? egy_ld_ accum = 1 ? e gy_tmr_mode = 0 ? rd_rst_en = 0 ? egy_pwr_en = 1 ? egy_time to the d esired number of samples ? f or the output, the x hr_hi register has enough resolutio n for most applications. to maintain perfect synchronization with the cf pulse output, the xhr_lo must be read as well because it is cleared at every egyrdy cycle. ? set the m aximum t ime before reading xhr_hi to preven t overflow with full - scale input s to 2 6 .4 sec . digital to frequency conve rsion cfx output many electricity meters are required to provide a pulse output that is proportional to the energy being accumulated, with a given pulse per kwh meter constant. the ade9078 includes four pulse outputs that are proportional to the energy accumulation in the cf1 through cf4 output pin s. a block diagram of the cfx pul se generation is shown in figure 65 . f ds p r e s e r v e d x w a t t x v a r x v a x f v a r r e s e r v e d x w a t t cfxsel[2:0] 1 0 0 0 1 1 0 0 0 0 0 1 0 1 0 1 0 1 1 1 0 x w a t t 1 1 1 0 0 1 termselx[0] phase a 0 0 1 termselx[1] phase b 0 0 1 termselx[2] + + + cfxsel[2:0] wthr cfx_ l t cf_ l tmr[18:0] cfxdis 4.096mhz digi t al t o frequenc y 512 cfxden cf_acc_clr 0 1 1 cfx pin pulse width config ade9078 cfx bits phase c v arthr va thr wthr v arthr va thr wthr wthr 1 0 0 0 1 1 0 0 0 0 0 1 0 1 0 1 0 1 1 1 0 1 1 1 14331-057 figure 65 . digital to frequency conversion for cf x table 20. cf x active low pulse width and duty cycle b ased on cfx_lt and cf_ltmr c f x _ lt active low pulse width for low frequencies (ms) active low pulse width for high frequencies when cfxden is e ven active low pulse width for high frequencies when cfxden is o dd behavior when entering no load 0 80 50% (1 + 1/cfxden) 50% if cfx is low, finish current pulse, return high . 1 cf_ltmr 6/clkin 1000 50% (1 + 1/cfxden) 50% if cfx is low, keep cfx low until the no load state is finished.
data sheet ade9078 rev. 0 | page 45 of 107 energy and phase selection the cfxsel[2:0] bits in the cfmode register select which type of energy to output on the cfx pin, including t otal active power, var, va, or fundamental var. the termselx bits in the compmode register select which phase energies to include in the cfx output. for example, with cf1sel = 000 and termsel1 = 111, cf1 indicates the total active power output of phase a, phase b, and phase c. to calibrate the phase a, phase b, and pha se c total active power accumulation at the same time, using cf1 for total awatt, cf2 for total bwatt, and cf3 for total cwatt, configure termsel1 = 010, and termsel2 = 100 . configuring the maximum cf pulse output frequency the xthr registers determine the maximum output rate from the digital to frequency converter. it is recommended to write xthr = 0x0010 0000. after the cfxden pulses are generated, a cfx pulse is issued. cfxden can range from 2 to 65,535. the relationship between the xthr, cfxden, and awa tt values is given in the following equation: ? ? ? ? ? ? ? ? = cfxden xthr awatt f cf dtof 512 (hz) where: f dtof is 4.096 mhz. awat t is the value at full scale, 20,823,646 . xthr is 0x0010 0000. cf x den is 2. the maximum recommended cf pulse output frequency is 7 9.4 khz. khz 4 . 79 2 512 0000 0010 x 0 20,823,646 10 096 . 4 (hz) 6 = ? ? ? ? ? ? ? ? = cf maximum the default cfx ulse out ut using ower on reset values of xthr and cfxden with full scale inuts is hz . xffff 0 512 ffff 0000 x 0 2024 10 0 . 4 (hz) = ? ? ? ? ? ? ? ? = cf maximum configuring the cf pulse width the pulse width is determined by the cfx_lt bit in the cf_lcfg register and the cf_ltmr regist er value. w hen cfx_lt = 0, the active low pulse width is set at 80 ms for frequencies lower than 1/(2 80 ms) = 6.25 hz. for higher frequencies, the duty cycle is 50% if cfxden is even or (1 + 1/cfxden) 50% if cfxden is odd. if cfx_lt is set to 1, the cf active low pulse width is cf_ltmr 6/clkin. the maxi mum cf_ltmr value is 327,680 = 0x0005 0000, which results in a 327,680/(6/clkin) = 80 ms pulse. cf_ltmr must be greater than zero. c fx pulse sign some applications must record positive and negativ e energy usage separately. to enable this operation, the sumx sign bits in the phsign register indicate whether the sum of the energy that went into the last cfx pulse was positive or negative. sumxsign = 0 if the sum of the energy that went into the cfx puls e is positive and equal to one if the sum of the energy was negative. additionally, the revpsumx bits in the status0 register and event_status register indicate if the cfx polarity changed sign. for example, if the last cf2 pulse was positive reactive ener gy and the next cf2 pulse is negative reactive energy, the revpsum2 bit in the status0 and event_status registe rs is set , which can be enabled to generate an interrupt on irq0 . clearing the cfx accumulator the user may want to clear out a partial cfx accumulation, for e xample, during the power up and initialization process. to clea r the accumulation in the digital to frequency converter and cfde n counter, write 1 to the cf_acc_clr bit in the config1 register . the cf_acc_clr bit automatical ly clears itself. disabling the cfx pulse output and cfx interrupt to disable the cfx pulse output and keep the cfx output high, write a one to the cfxdis bit in the cfmode register. if the cfxdis bit in the cfmode register is set, the cfx bit in status0 i s not set when a new cfx pulse is ready. note that the revpsumx bits, which indicate if cfx pulses were positive or negati ve, are not affected by the cfx dis setting. measurements (psm1) overview it is possible to tamper an energy meter by disconnecting the voltage inputs or the neutral. some regions require monitoring of the current inputs for several days after the voltage inputs to the meter have been cut, to check for this kind of tamper condition. the psm1 and psm2 operating modes in conjunction with psm3 enable low power consumption when checking for and billing for a tamper of this kind. psm1 enables fast measurement of irms, vrms, active power, and var with a reduced set of functions compared to psm0. to measure using psm1, chan ge the pm1 and pm0 pins to 0 and 1, respectively, to select the psm1 operating mode. then, configure the ic by writing to the xigain, xvgain, and xpgain registers. write to the run register to start the measure - ment s. to a chieve the speci fied accuracy, stay in psm1 mode for the time indicated in table 8 before reading the measurement results via the spi port (see the psm1 startup flow section for detailed information). after the psm1 results are read, change the pm1 and pm0 pins to 1 and 1 , respectively, to enter psm3 for one minute. then, enter psm1 by making pm1 and pm0 pins equal to 1 and 0 , respectively, to make measurements and begin the process again.
ade9078 data sheet rev. 0 | page 46 of 107 irms, vrms, and active power var the psm1 mode uses a different computation method than is done in psm0. these measurements are computed over 20 ms. table 1 gives the expected accuracy achieved 40.5 ms after setting the run register. figure 66 shows the current channel datapath for the ade9078 psm1. to calibrate these measurements, write the xigain, xvgain, and xpgain registers before writing the run register to start the calculation. note that this measurement is updated every 10 ms. there is an option to enable the rmsrdy interrupt in mask0 to indicate when this result is ready. this interrupt occurs every 10 ms; thus, several interrupts are required to reach 40 ms for the specified accuracy. note that these psm1 irms, vrms, active power, and var measurements are total bandwidth measurementsthey are done over the whole measurement bandwidth given in table 1. psm1 startup flow from psm2 and psm3 to start up psm1 from psm2 and psm3, follow these steps: 1. wait for the rstdone interrupt indicated by the irq1 pin going low. 2. configure the xigain, xvgain, and xpgain registers via the spi to calibrate the measurements. 3. wr ite r un = 1. 4. wait 40.5 ms, then read the results in the xirms, xvrms, xwatt, and xvar registers. 5. optionally, enable the rmsrdy interrupt in mask0 to indicate when this result is ready. this interrupt occurs every 10 ms; thus, several interrupts are required to reach 40 ms for the specified accuracy. psm1 startup flow from psm0 to start up psm1 from psm0, follow these steps: 1. if the voltage sags, the host microcontroller changes the pm1 and pm0 pins to 0 and 1, respectively, to change to the psm1 measurement mode. 2. the configured values in the xigain, xvgain, and xpgain registers remain valid. 3. wait 40.5 ms, then read the results in the xirms, xvrms, xwatt, and xvar registers. 4. optionally, enable the rmsrdy interrupt in mask0 to indicate when this result is ready. this interrupt occurs every 10 ms; thus, several interrupts are required to reach 40 ms for the specified accuracy. xigain hpf resampled waveform data range currentpeak detection reference - ? modulator v in in ade9078 current channe l (ia, ib, ic) sinc4 lpf 4:1 lpf1 xigainx phase comp waveform buffer integrator wf_src wf_cap_sel mten hpfdis inten iconsel* ib = ?ia ? ic current channel (xi_pcf) data range xi_pcf adc_ redirect mux note: iconsel only affects ib channel calculation psm1totalactiveandreactive powercalcul ation psm1 current rms calcul ations zx_src_sel zx detection not available in ade9078 psm1 14331-074 0v 0xfbff fb90 = ?67,110,000 0x0471 15c0 = +74,520,000 0v sinc4 + iir lpf (xi_lpf_dat) data range sinc4 output (xi_sinc_dat) data range 0x0400 0470 = +67,110,000 0xfb8e ea40 = ?74,520,000 0x0474 e650 = +74,770,000 0xfb8b 19b0 = ?74,770,000 16 ksps 4 ksps 4 ksps figure 66. current channel psm1 datapath
data sheet ade9078 rev. 0 | page 47 of 107 power accumulation figure 61 shows how awatt low-pass filtered active power samples are accumulated to provide an accurate active power value in the awatt_acc register. the sign of the phase a total active power accumulation is monitored in the revapa bit and interrupts can be enabled if the power changes sign. there are corresponding x_acc accumulations for each power on each phase and revx status bits in the status0 register to indicate if the power changes sign. power accumulation details figure 61 shows how awatt values are accumulated into an internal power accumulator and then are latched into the xwatt_acc register at a rate of pwrrdy. pwrrdy is set after (pwr_time + 1) 4 ksps samples accumulate. the power accumulation time can be calculated according to the following equation: internal power accumulation time (sec) = ? ? ? ? ? ? ? ? ? 4000 1_ time pwr the pwr_time[12:0] register allows up to (8191 + 1) = 8192 samples to be accumulated, which corresponds to 8192/4000 = 2.048 sec. internal power accumulation time (sec) = sec048.2 4000 18191 ? ? ? ? ? ? ? ? the internal power accumulator overflows at the same rate as the internal energy accumulator (see the internal energy register overflow rate section). accessing the user power registers the user accessible signed power accumulator is a 32-bit register that contains 32 msbs of internal power accumulator, x_acc, as shown in figure 67. 0 internal power accumulator 41 31 + + 31 0 awatt_acc f dsp 13 awatt 14331-058 figure 67. internal power register to awatt_acc calculate the expected awatt_acc according to the following formula based on the average awatt value: internal power accumulation = awatt ( pwr_time + 1) thus, awatt_acc is the 32 msbs, which can be calculated by rounding the following equation down to the nearest whole number: awatt_acc = rounddown( user power accumulation 2 ?13 ) where rounddown()is a function to round down to the nearest integer. for example, if 4000 samples of awatt are accumulated at 4 ksps with full-scale inputs, the expected value of awatt_acc is 0x009b 0003. user power accumulation = 20,823,646 (3999 + 1) = 83,294,584,000 awatt_acc = rounddown(83,294,584,000 2 ?13 ) = 10,167,795 = 0x009b 25f3 note that w/lsb varies with pwr_time accumulation time. power sign detection the revrpc, revrpb, revrpa, revapc, revapb, and revapa bits in the status0 register allow the user to monitor if the active or reactive power on any phase has changed sign. the pwr_sign_sel bit allows the user to select whether the power sign change follows the total or fundamental energies. to track total active power, set the revapx power sign status bits, pwr_sign_sel = 0. to track fundamental var on the revrpx bits, write pwr_sign_sel = 1. the cvarsign, cwsign, bvarsign, bwsign, avarsign, and awsign bits in the phsign register indicate whether the total or fundamental var selected in the pwr_sign_sel bit is positive or negative. the power signs are updated at the same time as the xwatt_acc, xvar_acc, and xfvar_acc registers and correspond to the sign of these registers. note that the power registers and signs are updated after the number of 4 ksps samples configured in the pwr_time register have elapsed, from 500 s to 2.048 sec. the power sign change indication in the revxpx bits are updated at the same time (see the power accumulation details section for more information). the ade9078 allows the user to accumulate total active power and var powers into separate positive and negative registers: pwatt_acc and nwatt_acc, pvar_acc and nvar_acc. this accumulation is done by evaluating the awatt, low-pass filtered active power every 4 ksps. if awatt is positive, it is added to the pwatt_acc accumulation. if awatt is negative, the absolute value is added to the nwatt_acc accumulation. a new accumulation from zero begins after the power update interval set in pwr_time has elapsed. the positive and negative total active power and total var from all three phases are added into the positive/negative active power and var accumulations.
ade9078 data sheet rev. 0 | page 48 of 107 awa tt interna l power accumul a t or awa tt , low p ass fi l tered active power positive active power, pw a tt_acc phase a active power sign indic a tion: a wsign, in phsign power u p d a te inte r v al set in pwr_time accumul a ted active power, awa tt_acc neg a tive active power, nw a tt_acc phase a active power sign change indic a tion: re v ap a, in s ta tus0 cleared after user writes s ta tus0 register with re v ap a bit se t , 14331-059 figure 68 . power accumulation and power sign zero - crossing detection the ad e9078 offers zero - crossing detection on the va, vb, vc, ia, ib, and ic input signals. the neutral current channel, in, does not contain a zero - crossing detection circuit. figure 69 shows the c urrent and v oltage c hannel d atapaths preceding zero - crossing detection. the zero - crossing circuit is the time base for resampling, line period, angle measurements , and energy accumulation using line cycle accumulation mode. the xv_pcf and xi_pcf are the v oltage and c urrent c hannel w aveforms processed by the dsp , which can be stored into the waveform buffer at a 4 ksps data rate (see the waveform buffer section for more information ) . current channe l vo lt age channe l zx detection lpf1 xvgain phase com p hpfdis zx_src_se l vconsel 1 vb = C v a C vc vb = v a C vc vb = C v a v a = v a C vb; vb = v a C vc; vc = vc C vb; xigain hpf xigainx phase com p integr a t or mten hpfdis inten iconsel 2 ib = Ci a C ic xv_pcf xi_pcf zx_src_se l 32 zx detection lpf1 2 iconse l on l y affects ib channe l calcul a tion 1 vconse l supports severa l 3-wire and 4-wire hard w are configur a tions 32 14331-060 100 011 010 001 000 figure 69 . voltage and current channel signal chain preceding zero - crossing detection
data sheet ade9078 rev. 0 | page 49 of 107 the zx_src_sel in the config0 register sets whether data going into the zero - crossing detection circuit comes before or after the high - pass filter, integrator , and phase compensation. by default, the data after phase compensation is used. note that the high - pass filter has settling time s given in ta ble 10 . thus, for a fast response, it is recommended to set zx_src_sel to look for a zero crossing before the high - pass filter. if the high - pass filter is disabled with hpfdis = 1 or if zx_src_sel = 1 , note that a dc offset on the input may cause the time between negati ve to positive and positive to negative zero crossings and positive to negative to negative to positive zero crossings to change, indicating that the zx detection does not have a 50% duty cycle. the current and voltage signals are low - pass filtered to remo ve harmonics. the low - pass filter, lpf1, has a corner of 85 hz and the equation is as follows : ( ) z z h = ia, ib, ic, o r v a, vb, vc 4.3ms a t 50hz 1 0.86 0v zx zx zx zx lpf1 output 14331-061 figure 70 . zero crossing detection on voltage and current channels to provide protection from noise, voltage chan nel zero - crossing events ( zxva, zxvb, and zxvc ) are not generated if the absolute value of the lpf1 output vo ltage is smaller than the threshold, zxthrsh. the current channel zero - crossing detection outputs ( zxia, zxib, and zxi c ) are active for all input s ignals levels. calcu late the voltage channel z e ro - crossing threshold, zxthrsh, from the following equation : zxthrsh = ( ) ( ) x n attenuatio lpf1 scale full at pcf v where v_pcf at full scale is 74,680,000d. lpf1 attenuation is 0.86 at 50 hz, and 0.81 at 60 hz, the gain attenuation of the lpf1 filter. x is the d ynami c range below which th e voltage channel zer o - crossing must be blocked . for example, assume that the full - scale input corresponds to 440 v rms. to prevent signals 100 lower than full scale (signals smaller than 4.4 v rms) from generating a voltage channel zero - crossing output, set zxt hrsh to 78d. ( ) ( ) = = zxthrsh additionally to revent false zero crossings after a zero crossing is generated 1 ms must ela se before the next zero crossing can be outut. combined voltage zero crossing phase a, phase b, and phase c voltage channel signals are combined to generate one zero - crossing signal, zx_comb, which is stable even if one or more phases drops out. the input to the zero - crossing detection is (va + vb ? vc)/2 with the signal chain corresponding to figure 71 . as described in the applications information section, the ade9078 can meter different polyphase configurations. the vconsel bits ind icate this selection. if vconsel is not equal to 0, the vb component in the combined zero - crossing circuit is set to zero. use the same precautions to prevent noise from generating zero - crossing interrupts on this output. as described in the zero - crossing detection section, signals below the zxthrsh threshold do not generate zxcomb outputs , and a minimum of 1 ms is required between zxcomb generations. zero - crossing output rates s even zero - crossing detection circuits monitor the ia, ib, ic, va, vb, vc , and the combined ( va + vb ? vc )/2 signal s . the zero - crossing detection circuits have two output rates: 4 ksps and 512 ksps . the 4 ksps zero - crossing signa l is used to calculate the line period, sent to the zxx bits in the status1 register , and is monitored by the z ero - c rossing t imeout, p hase s equence e rror d etection, r esampling , and e nergy a ccumulation functions. the 512 ksps signal is used for angle measur ements and is output on the cf3/zx pin if the cf3_cfg bit in the config1 register = 1 . table 21 indicates which zero - crossing edges (negative to positi ve and positive to negative) are used for each function and indicates what happens if a zero crossing is blocked because the input signal is below the user configured zxthrsh. the cf3/zx output pin goes from low to high when a negative to positive transiti on is detected and from high to low when a positive to negative transition occurs. the zx_sel bits in the zx_lp_sel register select the zero - crossing output used for line cycle energy accumulation and the zx output pin.
ade9078 data sheet rev. 0 | page 50 of 107 hpf zx detection, line period calcul a tion lpf1 phase com p hpfdis hpfdis hpfdis zx_src_se l a v_pcf phase a phase b phase c (va + vb C vc)/2 hpf zx_src_se l bv_pcf hpf phase com p zx_src_se l cv_pcf 2 vconsel[2:0] 0 phase com p 14331-062 f igure 71 . combined zero - crossing detection xx_pcf lpf1 zx_src_se l zx detection angle measurement zx output on cf3/zx pin f ds p clkin/24upd a te 32 zx indic a tion in s ta tus1 zero-crossing timeout phase sequence error detection resampling, energ y accumul a tion line period 14331-063 72 - table 21 . zero crossing use in other functions f un ct ions us i n g zer o cr ossing zx t ransitions u sed corresponding status1 b its selecting w hich phase to u se for measurement effect if zx d oes n ot o ccur zx i ndication in status1 r egister negative to positive and p ositive to negative zxia, zxib, zxic, zxva, zxvb, zxvc, and zxcomb n ot applicable the zxx bit is latched in status1. if it is cleared, it is not set again. a zxx interrupt does not occur. zero -c rossing t imeout negative to positive and p ositive to negative zxtova, zxtovb, and zxtovc n ot applicable zero - crossing tim eout is indicated by the zxtovx bits in th e status1 register and an interrupt can be enabled to occur. phase sequence error detection depends on vconsel setting seqerr n ot applicable if one to two zx events are missing, seqerr is generated. if all zx events are missing , the seqerr bit is not set. energy accumulation negative to positive and p ositive to negative n ot applicable zx_sel selects the zero - crossing output used for line cycle energy accumulation and zx output pin line cycle accumulation does not update . line period measurement negative to positive n ot applicable one line period measurement per phase (aperiod, bperiod, cperiod, comperiod) coerced to default val ue of 0x00500000 if selfreq = 0 for a 50 hz network or 0x0042aaab if selfreq = 1 for a 60 hz network.
data sheet ade9078 rev. 0 | page 51 of 107 functions using zero crossing zx transitions used corresponding status1 bits selecting which phase to use for measurement effect if zx does not occur resampling none not applicable lp_sel selects the phase voltage line period used as the basis for resampling calculation if the line period used for resampling is invalid because zero crossings are not detected or the calculation results in something outside a 40 hz to 70 hz range, the line period used for resampling is coerced to the default line period of 0x00500000 if selfreq = 0 for a 50 hz network, or 0x0042aaab if selfreq = 1 for a 60 hz network. angle measurements negative to positive not applicable not applicable the register does not update, keeps last value. zx output on the cf3/zx pin negative to positive and positive to negative not applicable zx_sel selects the zero- crossing output used for line cycle energy accumulation and the zx output pin the zx output remains at the current state, high or low. zero-crossing timeout the zero-crossing timeout feature alerts the user if a zero-crossing event is not generated after a user configured amount of time. if a zero crossing event is not received after zxtout/4 ksps clocks, the corresponding zxtox bit in the status1 register is set. for example, if zxtout is equal to 4000, if a zero crossing is not received on phase a for 4000/4 ksps = 1 sec, the zxtoa bit is set in the status1 register. the maximum value that can be written to the zxtout register is 0xffff/4000 = 16.38 sec. line period calculation the ade9078 line period measurement is performed by taking the values low-pass filtered by lpf1 as described in the zero- crossing detection section and then using the two values near the negative to positive zero crossing (pos1 and pos2) to calculate the exact zero-crossing point using linear interpolation. use this information to calculate the line period precisely, which is stored in the xperiod register. 4.3ms at 50hz ix,vx 0.86 0v lpf1 output pos2 pos1 pos2 x x x x pos1 14331-064 figure 73. line period calculation us ing zero-crossing detection and linear interpolation the line period, t l , can be calculated from the xperiod register, according to the following equation: (sec) 24000 1 16 ? ? ? xperiod t l similarly, the line frequency can be calculated from the xperiod register using the following equation: (hz) 1 24000 16 ? ? ? xperiod f l with a 50 hz input, the xperiod register is 0x0050 0000, 5242880d, and with a 60 hz input, it is 0x0042 aaaa = 4369066d. if the calculated period value is outside the range of 40 hz to 70 hz, or if the negative to positive zero crossings for that phase are not detected, the xperiod register is coerced to correspond to 50 hz or 60 hz, according to the setting of the selfreq bit in the accmode register. with selfreq = 0 for a 50 hz network, xperiod register is coerced to 0x0050 0000. if selfreq = 1, indicating a 60 hz network, the xperiod register is coerced to 0x0042 aaaa. the line period is calculated for the phase a, phase b, and phase c voltages and the combined voltage signal, as described in the combined voltage zero crossing section, and stored in the aperiod, bperiod, cperiod, and com_period, registers respectively. select the phase voltage line period to use as the basis for the resampling calculation using the lp_sel bits in the zx_lp_sel register or select a user configured value written in user_period using the uperiod_sel bit in the config2 register, as shown in figure 74. lp_sel 11 com_period cperiod bperiod aperiod resampling 1 1 not available in ade9078 psm1. user_period uperiod_sel waveform buffer 1 sinc4 output sinc4 + iir lpf output xi_pcf, xv_pcf ade9078 wf_cap_sel wf_src 14331-065 10 01 00 figure 74. line period selection for resampling the user period selection is helpful in applications where the user has another algorithm to determine the line frequency or if it is preferred to always assume a certain line frequency when resampling. user_period[31:0] has the same scaling as the xperiod registers. write user_period[31:0] to 0x00500000 for 50 hz and 0x0042aaab for 60 hz. angle measurement the ade9078 measures the time between zero crossings on each phase. this measurement determines if the system is balanced properly or to determine if there was an installation
ade9078 data sheet rev. 0 | page 52 of 107 error. it can be checked if the phase angles correspond to the ones in the phasor diagrams given in the applications information section. the times between negative to positive zero crossings are measured using a clkin/24 = 12.288 /12 = 512 khz clock. the time between the zero - crossing on phase a and phase b is stored in the angl_va_vb register. the resolution of the an glx_x2x register is (1/512000)/20 ms 360 = 0.03515625 at 50 hz. the time between the zero crossing on phase b and phase c is stored in the angl_vb_vc register and the time in between the zero crossings on phase a and phase c is stored in the angl_va_vc register, as shown in figure 75. phase a phase b phase c angl_ v a_vb angl_vb_vc angl_ v a_vc 14331-066 figure 75 . voltage to voltage phase angle the a ngle in degrees can be calculated from the following equation with a 50 hz line period: angle (degrees) = angl_va_vb 0.03515625/lsb for a 4 - wire w ye configuration, the expected angl_va_vb and angl_vb_vc is 120 /0.03515625 = 3413d. note that the expected angl_va_vc from phase a voltage to phase c voltage is 24 0 /0.03515625 = 6826d, which corresponds to a 120 angle between phase c and phase a. th e current to current zero crossings are also measured. this measurement is done similarly to the voltage to voltage phase angle described previously, except the current channel zero crossings are used as the reference. the time between the zero crossing on phase a and phase b is stored in the angl_ia_ib register. the time between the zero crossing on phase b and phase c is stored in the angl_ib_ic regis ter and the time in between the zero crossings on phase a and phase c is stored in the angl_ia_ic register. the voltage to current phase angles are measured as well. use t hese measurements to determine the power factor at the fundamental. angl_va_ia reflec ts the phase angle between the phase a voltage and current , as shown in figure 76. angl_vb_ib holds the phase b voltage to current phase angle , wh ereas angl_vc_ic holds the phase c voltage to current phase angle. phase a current angl_ v a_i a phase a volt age 14331-067 figure 76 . voltage to current phase angles note that if the magnitude of the voltage channel is below the user configured zero - crossing threshold, the zero - crossing ou tput for that phase is not generated. in this event, the corresponding anglx_x2x measurements are not updated the last value remains in the register. the current channel does not have these thresholds. w hen low input signal level s occur , spurious zero - cros sing events may be generated on the current channel , which results in anglx_i2i and anglx_v2i readings that are not meaningful. phase sequence error detection 4 - wire wye and 4 - wire delta for 4 - wire wye and 4 - wire delta meters, the normal phase sequence is shown in figure 77. zxc zxb phase a phase b phase c a,b,c phase vo lt ages after lpf1 zx a norma l phase sequence seqerr = 0 14331-068 figure 77 . 4 - wire wye and 4 - wire delta normal phase sequence for a 4 - wire wye or 4 - wire delta system, vconsel = 000, 010, or 011 as described in the applications information section. in t hese 4 - wire systems, the negative to pos itive transitions on zxva, zxvb, and zxvc are monitored to determine if there is a phase sequence error as shown in figure 79 . to detect a phase sequen ce error, set how many sequences to observe in the seq_cyc register. i t is recommended to set seq_cyc to 1.
data sheet ade9078 rev. 0 | page 53 of 107 figure 78 shows a phase sequence er ror for a 4 - wire w ye or 4 - wire d elta due to a wiring or installation error. zxa zxb phase sequence error (seqerr = 1) seqerr a,b,c phase voltages after lpf1 zxc 14331-069 figure 78 . 4- w ire wye and 4 - w ire delta phase sequence error (wiring error) figure 79 shows that in an installation with the normal phase sequence, a phase sequence error is generated if a phase voltage drops below the zxthrsh value . zxc zxb a,b,c phase voltages after lpf1 phase sequence error zxc zxb zxc zxb seqerr zxa 14331-070 figure 79 . 4- w ir e wye, 4 - w ire delta phase sequence error from a phase voltage d ropping b elow zxthrsh with seq_cyc = 1 3 - wire delta for a 3 - wire delta system, vconsel = 001 or 100 as described in th e applications information section. in a 3 - wire delta system, the zxvc and zxva positive to negative (zxx_pos) and negative to positive (zxx_neg) transitions are monitored to detect a phase sequence error. figure 80 shows t he normal phase sequence for a 3 - wire delta with vconsel = 001. zxa_pos zxc_neg phase a = vab phase c = vcb va,vc after lpf1 zxc_pos normal phase sequence seqerr = 0 zxa_neg 14331-071 figure 80 . 3- w ire delta normal phase sequence write seq_cyc to indicate how many consecutive incorrect transitions must be observed before raising the seq_err interrupt. it is recommended to set seq_cyc to 1. figure 81 shows an installation error for 3 - wire delta that results in a detected p hase s equence e rror. seqerr seqerr set t o 1 14331-072 zxc_pos zxa_neg phase c = vcb phase a = v ab v a, vc after lpf1 zxa_pos zxc_neg figure 81 . 3- wire delta phase sequence error (wiring error) figure 82 shows that in an installation with the normal phase sequence, a phase sequence error is generated if one of the phase voltage s drops below the zxthrsh value . zxc_neg zxa_pos phase c phase a v a, vb, vc after lpf1 zxa_neg seqerr zxa_neg zxa_pos zxa_pos zxa_neg irq1 seqerr set to 1 write seqerr = 1 to acknowledge this event and clear seqerr 14331-073 zxc_pos figure 82 . 3- wire delta phase sequence error from a phase voltage d ropping b elow zxthrsh with seq_cyc = 1 peak detection the ade9078 records the peak value measured on the current and voltage channels, from the xi_pcf and xv_pcf waveforms. the peaksel bits in the config3 register allow the user to select which phases to monitor. set peaksel , bit 2 to monitor phase c ; peaksel , bit 1 for phase b ; and peaksel , bit 0 for phase a. set peaksel = 111b to monit or all three phases. the ipeak register stores the peak current value in ipeakval , bits [23:0] and indicates which phase currents reached the value in the ipphase bits. ipeakval is equal to xi_pcf/2 5 . ipphase, bit 2 indicates that phase c had the peak valu e ; ipphase, bit 1 indicates phase b ; and ipphase , bit 0 indicates phase a.
ade9078 data sheet rev. 0 | page 54 of 107 similarly, vpeak stores the peak voltage value in vpeakval , bits [23:0]. vpeakval is equal to xv_pcf/2 5 . vpphase , bit 2 indicates that phase c had the peak voltage value ; vpphase , bit 1 indicates phase b ; and vpphase , bit 0 indicates phase a. when the user reads the ipeak register, its value is reset. the same is true for reading vpeak. measurements (psm2) overview it is possible to tampe r with an energy meter by disconnecting the voltage inputs or the neutral. some regions require monitoring of the current inputs for several days after the voltage inputs to the meter have been cut, to check for this kind of tamper conditio n. the psm1 and psm2 operating modes in conjunction with ps m3 enable low power consumption when checking for and billing for a tam per of this kind. to use this feature, first write the psm2_cfg register to configure the current threshold to compare the input current level to and for how long to perform the detecti on while in either psm0 or psm1 operati ng modes. then, change the pm1 and pm0 pins to 1 and 0, respectively, to select the psm2 operating mode. to achieve the specified accura cy, stay in psm2 mode for the time indicated in table 8 before checking the irq0 and irq1 pins to see if a tamper has occurred. if no tamper ing is detected, change the pm1 and pm0 pins to 1 and 1 , respectively, to enter psm3 for one minute. then, enter psm2 by making pm1 and pm0 pins to 1 and 0 , respectively, to check for tamper and begin the process again. low power comparator in the psm2 operating mode, the ade9078 enters a low power state where only a low power comparator is active. the 1.8 v ldos, adcs, dsp , and crystal oscillator are turned off. in this mode, the input currents (ia, ib, ic) are compared against a user selected level set in psm2_cfg register. the irq0 and irq1 pins indicate whether any of the three currents exceeds the threshold. the amount of time allowed for the detec tion is decided by th e user and set in the lpl ine bits of the p sm2_cfg register. the measurement time is the period of (lpline + 4)/50 sec. the ade9078 indicates that a tamper is detected if at least lpline + 1 peak s are obtained on a current channel. the maximum allowed value in lpline is 0x0a. for example, if lpline = 2, six cycles of measurement time and three peaks are required on a given channel to indicate a tamper event. the level to compare the current against is set in the psm2_cfg register, pkdet _ lvl bits, as shown in table 22. table 22. psm2 current peak detect thresholds pk det_lvl threshold level 0 144:1 1 271:1 2 377:1 3 498:1 4 578:1 5 660:1 6 764:1 7 845 :1 8 970:1 9 1100 :1 10 1196 :1 11 1312 :1 12 1371 :1 13 1464 :1 14 1559 :1 15 1629 :1 after the configured measurement time set and (lpline + 4)/50 sec has elapsed, the irq0 and irq1 pins indicate if a tamper has occurred. if irq0 is low, all the currents have had less than lpline + 1 peaks ; no tamper is detected. if irq1 is low, at least one current was above lpline + 1 peaks and a tamper is detected. after the tamper is detected, switch to psm1 power mode by changing the pm1 and pm0 pins to 0 and 1 , respectively, to measure key measurements quickly: irms, vrms, active power , va r , va , and others (see the measurements (psm1) section for more information ) .
data sheet ade9078 rev. 0 | page 55 of 107 key features flexible waveform bu ffer w ith resampling an integrated flexible waveform buffer stores samples at a fixed data rate or a sampling rate that varies based on the line frequency to ensure 64 points per line cycle. these two options make it easy to implement harmonic analysis in an ext ernal processor according to iec 61000 - 4 - 7. there is a choice of data rate for the fixed data rate samples: 4 ksps or 16 ksps (s ee the waveform buffer section for more details). multip oint phase/gain cali bration to provide more accurate measurements when using current transformers, the ade9078 provides a multipoint gain and phase calibration option. if selected, the user can enter unique gain and phase calibrations for up to five regions of ct operation. use the current rms ( irms ) value to select the current region of operation and to determine which gain and phase calibration to apply ( s ee the multipoint gain and phase calibration section for more details). rms of sum of instan taneous curren ts measurement the ade9078 offers a n rms measurement of the sum of instanta - neou s currents. use t his measurement to estimate the neutral current rms if a neutral current sensor is not available. if a neutral current sensor is used, the rms of the sum of instantaneous currents can include ia + ib + ic in. ideally, ia + ib + ic in = 0 . the rms of the sum of instantaneous currents is compare d to a user configured threshold. if it is greater than the threshold, a mismatch interrupt is generated. this mismatch indication can help detect earth currents or tamper, which is a safety hazard ( s ee the neutral current rms, rms of sum of instantaneous currents section for more details). tamper modes two power modes are provided to enable detection of meter tampering: psm2 uses a low power comparator to compare current channels to a threshold and indicates whether it i s exceeded on the irq0 and irq1 outputs; and psm1 enables fast measurement of current and voltage rms, active power, and var during a tamper. the pm0 and pm1 pins control which power supply mode is selected: psm0 ( n ormal m ode), psm1 ( t amper m easurement m ode), psm2 ( t amper d etection m ode), or psm3 ( i dle). the user application manages the pm0 and pm1 pins to put the ade9078 in psm1 or psm2 modes for the requ ired time to perform the measurement or detection. then , the user application changes pm0 and pm1 to put the ade9078 in psm3, idle mode, until the cycle must b egin again usually once per minute (see the power modes section for more details). power factor the power factor (pf) is calculated for each phase and is updated a t the user configured power update rate , which can be up to 1 sec. pf is the total active power divided by the total apparent power. to determine the quadrant, use the sign in the reactive power register ( s ee the power factor section for more details). zero - crossing timeout det ection z ero - crossing timeout detection is provided on each phase voltage to indicate if the phase voltage has been low for a user configured time perio d. an interrupt is generated if this event occurs (see the zero - crossing timeout section for more details). line period measurem ent the ade9078 offers a highly accurate line period measurement that provides 0.001 hz resolution. it is possible to measure the line period on all three phases as well as a combined signal that reflects the line period, regardless of if ther e is one or many phases present ( s ee the line period calculation section for more details). angle meas urement voltage to voltage, voltage to current, and current to current angles are measured simultan eously with 0.036 resolution at 50 hz. these measurements a llow fundamental power factor calculations and check s of the balance of the system ( see the angle measurement section for more details). phase sequence error detection voltage channel zero crossings are monitored to indicate if a phase sequence er ror occurs in both 3 - phase , 4 - wire ( w ye) , and 3 - wire (delta) connections (see the phase sequence error detection section for more details).
ade9078 data sheet rev. 0 | page 56 of 107 quick start there are a few important steps to note when using the ade9078 ic. for most applications, ensure that the pm1 and pm0 pins a re low to enter normal measurement mode ( psm0 ) . the following initialization sequence is recommended: 1. wait for the rstdone interrupt , indicated by the irq1 pin going low. 2. configure the xigain, xvgain, and xpgain registers via the spi to c alibrate the measurements. 3. if other calibration values are required, for example , to improve rms performance at low input signal levels, write these registers. 4. if the cfx pulse output is used, configure the cfxden and xthr registers. 5. configure the expected fundamental frequency (50 hz or 60 hz network) in the selfreq bit and write vlevel = 0x117514 . 6. if a rogowski coil sensor is used, write the inten bit in the config0 register to enable the digital integrator on the ia, ib, and ic channels . t o enable the digital integrator on the neutral current, in , channel, set the ininten bit. a dditionally, write dicoef = 0xffffe000 to configure the digital integrator. if current transformers are used, inten and ininten in the config0 register must = 0 . 7. if the service bring measured is something other than 4 - wire wye, see table 24 to determine how to configure iconsel and vconsel in the accmode regist er . 8. write a 1 to the run register. 9. write a 1 to the ep_cfg register . the ade9078 ic sampling capacitors vary device to device ( see table 1 ) . for this reason, gain calibration is required to be able to accurately measure connected loads. if a current transformer senso r is used, phase calibration is required to remove any device t o device variation in the phase error to accurately measure loads over power factor. use the following e xample to determine if the ade9078 ic is correctly measuring the input voltage signal. in this example, a 1 m ? and 1 k ? resistor divider network measure s the voltage between the phase a voltage and the neutral. if the input signal is 240 v rms, the expected voltage at the input to the ade9078 ic is 240 v rms 1000/(1000 + 1 , 000 , 000) = 0.239 7 v rms. the ade9078 adc full - scale input is 1 v, 0. 707 v rms. th us, 0.239 7 v rms/ 0. 707 v rms = 33.9% of full scale. it is recommended to scale the nominal voltage input to about ? of full scale to allow room for overvoltage events. as described in the filter - based total rms section, the full - scale voltage rms register output reading is given as 52,866,837 d. th us , with this 33.9% of full - scale input, the expected vrms register reading is 17,921,858 . n ote that the actual xvrms register reading var ies based on the external component gain error, combined with the ade9078 ic device to device gain error. a ssume that 18,000,000d is read when the 240 v rms loa d was applied. th us, there are 18 , 000 , 0 00 output codes per 240 v rms , which means there are 75,000 output codes per volt . t ake the xvrms register reading and divide by 75 , 00 0 to determine the voltage in v olts. volts = xvrms /75 ,000 a similar exercise can be performed to determine if the ade9078 ic is correctly measuring the input power. for example, if the same 240 v rms signal is applied along with a 10 a load, the applied power is 240 v 10 a = 2.4 kw . a ssum ing that the 10 a load is connected to a current transformer with 1000:1 turn ratio on the secondary side, the current is 10 ma. assume a center tapped burden resistor is used so that there is 10 ? total burden resistance . th us, 10 ma 10 ? yields a 0.1 v rms signal. the ade9078 ic allows full - scale inputs of 1 v, 0. 707 v rms , which means that the 10 a input is 0.1 v rms/ 0. 707 v rms = 14.1% of full scale. for the active power measurement, with a 240 v 10 a load, the ade9078 ic sees 33.9% of full scale on the voltage side and 14.1% on the current side, so 33.9% 14.1% = 4.8% of the full - scale output power. as described in the total active power section, the xwatt register reads 20,823,646 with full - scale inputs. th us, with this load applied, 4.8% 20,823,646 = 99 9 ,535 is the expected register reading. a ssume that 1,000,000 d is read when the 240 v rms, 10 a load i s applied. th us, there are 1,000,000 output codes per 2.4 kw , which mean s there are 416,667 output codes pe r k w. read the xwatt register and divide by 416,667 to determine the power in w atts. watts = xwatt /416,667
data sheet ade9078 rev. 0 | page 57 of 107 applications informa tion t he voltage and current waveforms of a polyph ase system are defined in the following equations : t) ( (t) = v a sin 2 ) t ( (t) = v b 120 C sin 2 ) t ( (t) = v c + 120 sin 2 ) t ( (t) = i a C sin 2 ) t ( (t) = i b 120 C C sin 2 ) t ( (t) = i c + 120 C sin 2 c b a n v an i a vcn ic 270 lagging 90 lagging 18 0 0 ib vbn 14331-021 figure 83 . 4- w ire wye service vector diagram figure 84 to figure 87 show comm on metering configurations: 3 - wire delta, 4 - wire delta , and 3 - wire residential and network . the ade9078 can also measure multiple single - phase circuits. 18 0 270 lagging 90 lagging 0 c b a vb a v ac v c b i a ic ib 14331-022 figure 84 . 3- w ire delta service vector diagram 270 lagging 90 lagging 18 0 0 n c b a v an i a vcn ic ib vbn 14331-023 85 4- 270 lagging 90 lagging 18 0 0 n b a 14331-024 86 3- - 270 lagging 90 lagging 18 0 0 b a n 14331-025 87 3- the phasor diagrams show how the voltages and currents are related in time. figure 88 shows the 4 - wire w ye voltage phase sequence in time, corresponding to the figure 83 p hasor diagram and equations for v a , v b , and v c , provid ed previously in this section . phase a van phase b vbn phasec vcn 14331-026 figure 88 . 4- wire wye, voltage phase sequence in t ime
ade9078 data sheet rev. 0 | page 58 of 107 non - blondel c ompliant m eters blondels theorem states that there must be n ? 1 measurin g elements in a meter, where n is the number of the wires of the electric system . in this way, a blondel compliant 4 - wire wye or 4 - wire delta measures three voltages and three currents. in a 3 - wire delta service, at least two voltages and two currents must be measured to be blondel compliant . iec meter forms are all blondel compliant. ansi has some meter forms that are not blondel compliant, meaning that there are fewer than n ? 1 elements, so that in a 4 - wire wye or 4 - wire delta configuration , two voltage s and three currents are measured. the ade9078 has provisions to deal with no n - blondel compliant meter forms . use the vconsel bits in the accmode register to selec t what calculation to use for v b based on the v a and v c signals. table 23. non - blondel compliant meter forms service type non - blondel compliant ansi meter form vconsel v b c alculation 4 - w ire wye, two v oltages, three c urrents 6s, 7s, 14s, 29s, 36s, 46s, 76s 010 v b = ? v a ? v c 4 - w ire delta, two v oltages, three c urrents 8s, 15s, 24s 011 v b = ? v a applying the ade9078 to a 4 - wire wye s ervice for the highest level of performance when measuring a 4 - wire wye service, co nnect the n eutral to ground, as sho wn in figure 89 . for this configuration, vconsel = 000. vap vbp vcp van agnd dgnd neutral vbn vcn vbn vb 220v C120 C120 0.353v 220v 120 120 0.353v phase c vcn vc phase a phase b van va 220v 0 220v C120 220v 120 phase c phase a phase b 220v 0 0.353v 0 vconsel = 000 va, vb, vc 14331-027 figure 89 . 4- w ire wye, neutral c onnected to ground alternatively, a series impedance can be used on t he n eutral , as shown in figure 90 , which can be advantageous if an isolated power supply is used . note that this configuration has poor performance if the phase voltages are not balanced. for more information, see the an - 1334 application note . for this configuration, vconsel = 000. neutral vap vbp vcp van agnd dgnd vbn vcn vbn vb 220v C120 C120 0.353v 220v 120 120 0.353v phase c vcn vc phase a phase b va 220v 0 220v C120 220v 120 phase c phase a phase b 220v 0 0.353v 0 vconsel = 000 va, vb, vc neutra l a ttenu a tion network 14331-028 figure 90 . 4- w ire wye, series impedance on the neutral phase sequence error detection is performed based on the expected abc sequence (see the phase sequence error detection section fo r more information ) . to calculate the over al l power consumed by the system (active, reactive , and apparent), add the contribution from the phase a, phase b , and phase c accumulation s.
data sheet ade9078 rev. 0 | page 59 of 107 applying the ade9078 to a 3 - wire delta s ervice for the highest level of performance when measuring a 3 - wire delt a service, connect phase b to ground, as shown in figure 91 . for this configuration, write vconsel = 00 1 in the accmode register . then , v b = v a ? v c and the ade9078 calculates the vac potential in the bvrms register . to calculate the current flowing th rough i b from the i a and i c measurements, set iconsel = 1 in the accmode register so that i b = ? i a ? i c . vbc 220v vc 90 0.353v 90 3 vba 220v va 30 0.353v 30 3 vac 220v vb 150 0.353v 150 3 vconsel = 001 va, vb, vc vap vbp vcp van agnd dgnd vbn vcn 220v C120 220v 120 phase c phase a phase b 220v 0 14331-029 figure 91 . 3- wire delta, phase b c onnected to ground note that for this 3 - wire d elta, phase b connected to g round configuration, the phasor diagram of the av_pcf, bv_pcf , and cv_pcf waveforms inside the ade9078 ic , shown in figure 92 , is shifted comp ared to the service diagram given in figure 84. cv_pcf ai_pcf a v_pcf ci_pcf bi_pcf bv_pcf vconse l = 1 18 0 0 270 lagging 90 lagging 14331-030 figure 92 . phasor diagram of xv_pcf and xi_pcf w aveforms i nside the ic with 3 - w ire delta with phase b as g round a nd vconsel = 001 to use the same pcb for both 4 - wire w ye and 3 - wire d elta circuits, another option is to wire phase b to the n eutral terminal of the meter, keeping the same circuit as used in figure 89 o r figure 90. note that vconsel bits in the accmode register must be set to 001 if it is desired to obtain the vac rms value , which is calculated in the bvrms register , and to use the correct phase sequence detection method for the 3 - wire delta configuration . to calculate the current flowin g through ib from the ia and i c measurements, set iconsel = 1 in the accmode register s o that i b = ? i a ? i c . alternatively, a series impedance can be u sed on phase b , as shown in figure 93 . this configuration can be advantageous if an isolated power supply is used ; however, it has poor performance if the phase voltages are not balanced. use vconsel = 100 with this configuration so that v a = v a ? v b ; v b = v a ? v c ; and v c = v c ? v b . to calculate the current flowing through i b from the i a and i c measurements, set iconsel = 1 so that i b = ? i a ? i c .
ade9078 data sheet rev. 0 | page 60 of 107 vbc 220v vc 90 0.353v 90 3 vba 220v 30 0.353v 30 3 vac 220v vb 150 0.353v 150 3 vconsel[2:0] = 100 calculated va, vb, vc vap vbp vcp van agnd dgnd vbn vcn 220v ?120 220v 120 phase a phase b 220v 0 14331-031 figure 93. 3-wire delta, series impedance on phase b and vconsel = 100 the v a , v b , and v c waveforms computed inside the ade9078 for the 3-wire delta with series impedance on phase b and vconsel = 100 are shown in the time domain in figure 93 and correspond to the phasor diagram shown in figure 92. phase sequence error detection is performed with the expectation that the vc waveform leads v a (see the phase sequence error detection section for more information). in a blondel compliant 3-wire delta meter, only the overall power consumed by the system is meaningful; the individual phase powers are not meaningful because a line current is multiplied by a line to line voltage. to calculate the overall power consumed by the system (active, reactive, and apparent), add the contribution from phase a and phase c. applying the ade9078 to a non-blondel compliant, 4-wire wye service to u s e t he ade9078 in a non-blondel compliant 4-wire wye service, such as for ansi meter forms 6s, 7s, 14s, 29s, 36s, 46s, 76s, the phase a and phase c voltages are measured and the phase b voltage is calculated, v b = v a ? v c . all three phase currents are measured. for this configuration, write vconsel = 010 and connect as shown in figure 94. vap vbp vcp van agnd dgnd neutral vbn vcn vbn vb 220v ?120 ?120 0.353v 220v 120 120 0.353v phase c vcn vc phase a phase b van va 220v 0 220v ?120 220v 120 phase c phase a phase b 220v 0 0.353v 0 vconsel = 010 va, vb, vc 14331-032 figure 94. non-blondel compliant 4-wire wye the phasor diagram follows figure 83. phase sequence error detection is performed based on the expected abc sequence (see the phase sequence error detection section for more information). to calculate the total power (active, reactive, and apparent), add the contribution from phase a, phase b, and phase c. applying the ade9078 to a non-blondel compliant, 4-wire delta service to use the ade9078 in a non-blondel compliant 4-wire delta service, such as for ansi meter forms 8s, 15s, and 24s, measure the phase a and phase c voltages and calculate the phase b voltage, v b = ?v a . all three phase currents are measured. for this configuration, write vconsel = 011 in the accmode register and connect as shown in figure 95.
data sheet ade9078 rev. 0 | page 61 of 107 vap vbp vcp van agnd dgnd neutral vbn vcn vbn vb 220v ?150 ?150 0.353v 220v 120 120 0.353v phase c vcn vc phase a phase b van va 220v 30 220v ?150 220v 120 phase a phase b 220v 30 0.353v 30 vconsel = 011 va, vb, vc 14331-033 figure 95. non-blondel compliant 4-wire delta the phasor diagram is shown in figure 85. phase sequence error detection is performed based on the expected abc sequence (see the phase sequence error detection section for more information). to calculate the total power (active, reactive and apparent), add the contribution from phase a, phase b, and phase c. service type summary to summarize, the ade9078 can be used in many different configurations to measure 4-wire wye, 4-wire delta, and 3-wire delta installations. table 24 summarizes which vconsel and iconsel settings to use for each configuration. table 24. service type and vcon sel and iconsel setting summary service type ground reference figure reference no. of voltage sensors required vconsel setting no. of current sensors required iconsel setting 4-wire wye neutral figure 89 3 000 3 0 isolated figure 90 3 000 3 0 3-wire delta phase b figure 91; figure 89 with phase b tied to neutral 2 001 (v b = v a ? v c ) 2 0: i b has current sensor 1: i b = ?i a ? i c isolated figure 90 with phase b tied to neutral 2 001 (v b = v a ? v c ) 2 0: i b has current sensor 1: i b = ?i a ? i c isolated figure 93 2 100 (v a = v a ? v b ; v b = v a ? v c ; v c = v c ? v b ) 2 0: i b has current sensor 1: i b = ?i a ? i c 4-wire delta neutral figure 89 (note that the va and vb phasor diagram follows figure 85) 3 000 3 0 4-wire wye, non-blondel compliant neutral figure 94 2 010 (v b = v a ? v c ) 3 0 4-wire delta, non- blondel compliant neutral figure 95 2 011 (v b = ?v a ) 2 0: i b has current sensor 1: i b = ?i a ? i c 3-wire single-phase neutral not applicable 1 or 2 000 1 to 2 0 3-wire network neutral not applicable 2 000 2 0 multiple single- phase circuits neutral not applicable 3 000 3 0
ade9078 data sheet rev. 0 | page 62 of 107 accessing on-chip data spi protocol overview the ade9078 has a spi-compatible interface, consisting of four pins: sclk, mosi, miso, and ss . the ade9078 is always a spi slaveit never initiates spi communication. the spi interface is compatible with 16-bit and 32-bit read/write operations. see the register information section for information about the length of each register. figure 96 shows the connection between the ade9078 spi and a master device that contains a spi interface. ade9078 spi master mosi miso sclk ss mosi miso sck cs 14331-075 figure 96. connecting the ade9078 slave spi port to a master spi device the ss pin is the chip select input. it starts the spi communication with the ade9078 . there are three parts to the ade9078 spi protocol: first a 16-bit command is sent, which indicates whether to perform a read or write operation and which register to access. this is followed by the 16- or 32-bit data to write, in the case of a spi write, or the data read from the register, in the case of a spi read operation. finally, in the case of a spi read operation, a cyclic redundancy check (crc) of the register data follows, unless the address is in a region that supports burst reading, in which case the data from the next register follows (see the spi burst read section for more information). the ss input must stay low for the whole spi transaction. bringing ss high during a data transfer operation aborts the transfer. a new transfer can be initiated by returning the ss logic input low. it is not recommended to tie ss to ground because the high to low transition on ss starts the ade9078 spi transaction. data shifts into the device at the mosi logic input on the falling edge of sclk, and the device samples the input data on the rising edge of sclk. data shifts out of the ade9078 at the miso logic output on the falling edge of sclk and must be sampled by the master device on the rising edge of sclk. the msb of the word is shifted in and out first. miso has an internal weak pull-up of 100 k, making the default state of the miso pin high. it is possible to share the spi bus with multiple devices, including multiple ade9078 devices, if desired. the ade9078 is compatible with the following microcontroller spi port clock polarity and phase settings: cpol = 0 and cpha = 0 (typically mode 0) or cpol = 1 and cpha = 1 (typically mode 3). note that the default state of the mosi pin depends on the master spi device. in figure 97, figure 98, and figure 100, it is assumed to be high (logic 1). s cl k mosi cmd_hdr = 0x6078 miso airms at 0x607 32 bits airms at 0x607 32 bits birms at 0x608 32 bits 31 ss crc, 16 bits 0 15 0 15 0 31 0 miso 31 0 burst_en = 0 address 0x500 to address 0x6ff burst_en = 1, address 0x500 to address 0x6ff 14331-076 figure 97. spi read protocol examplecrc or next data can follow 31 s clk mosi miso ss cmd_hdr = 0x00b0 avgain at 0x00b 0 15 0 14331-077 figure 98. spi write protocol example the maximum serial clock frequency supported by this interface is 10 mhz. the spi read/write operation starts with a 16-bit command (cmd_hdr), which contains the following information: ? cmd_hdr, bits[15:4] are the 12 msbs of the command header, and contains the address of the register (addr, bits[11:0]) to be read or written. ? cmd_hdr, bit 3 is the bit that specifies if the current operation is read/write. set this bit to 1 for read and 0 for write. ? cmd_hdr, bits[2:0] are required for internal chip timing and can be 1s or 0s. note that these bits are read back as 000 in the last_cmd register. figure 99 shows the information contained in the command header. 15 32 0 addr[11:0] r/w xxx read = 1 write = 0 don?t care bits a ddress to be a ccessed 14331-078 figure 99. command header, cmd_hdr, bits[15:0]
data sheet ade9078 rev. 0 | page 63 of 107 spi write a write operation using the spi interface of the ade9078 is initiated when the ss pin goes low and the ade9078 receives a 16- bit command header (cmd_hdr) , with cmd_hdr , bit 3 = 0. the 16- bit or 32 - bit data to write follows the command header, with the msb first. after the last bit of data has been clocked out, the master bring s the ss line high to release the spi bus. it is recommended to have the sclk line idle high. spi read a read operation using the spi interface of the ade9078 is initiated when the ss pin goes low and the ade9078 receives a 16 - bit com - man d header (cmd_hdr) , with cmd_hdr , bit 3 = 1 . the 16- bit or 32 - bit data from the register follows the command header, with the msb first. t he crc of the register data is appended if ? burst_en = 0 and the address is within the range of address 0x000 to address 0x 6ff . ? burst_en = 0 and t he address is in the waveform buffer, address 0x800 to address 0xfff and burst_chan = 1111b . the ade9078 provides a spi b urst r ead functionality instead of sending the crc, the following data is sent from the next address if these conditions apply (see the spi burst read section for more information ) : ? burst_en = 1 and the address is within the range of address 0x500 to address 0x516 , address 0x600 to address 0x 63c , or address 0x680 to address 0x 6bc. ? the address is within the range of address 0x800 to address 0xfff and burst_chan is not equal to 1111b. if none of these cases apply, and extra clocks are se nt, the original read data is resent. table 25 summarizes wh at data is sent after the data from the register addressed in the cmd_hdr it varies based on the address being accessed and the burst_en selection. table 25. data c locked o ut a fter a ddressed d ata in spi read o peration address burst_en = 0 burst_en = 1 0x000 to 0x 4ff crc same data is resent 0x500 to 0x 6ff crc next address 0x800 to 0x fff (waveform buffer) if burst_chan = 1111, crc ; otherwise, n ext address if burst_chan = 1 111, the same data i s resent ; otherwise, n ext address i f this information is not needed in the application , t he ss line can be brought high before clocking out the crc . after the last bit of data , or crc, is clocked out, the master must bring the ss line high to release the spi bus. then the ade9078 stops driving miso and enables a 100 k ? weak pull - up. it is recommended to have the sclk line idle high. an example of what happens when reading the avgain register, a ddress 0x00b, when burst_en = 0 and 1, is given in figure 100 . sclk mosi cmd_hdr = 0x00b8 miso a vgain a t 0x00b ss crc, 16 bits 0 15 0 0 31 0 miso 0 burst_en = 0 address 0x000 t o address 0x6ff burst_en = 1, address 0x000 t o address 0x6ff a vgain a t 0x00b a vgain a t 0x00b 14331-079 figure 100 . spi read protocol example w here the f ollowing d ata i s the crc or the i nitial d ata i s r epeated spi burst read spi b urst read allows multiple registers to be read after sending one cmd_hdr. after the register data has been clocked out, the ade9078 auto - increment s the address and start s clocking out the data f rom the next register address. spi b urst read access is available on registers with addresses ranging from address 0x5 00 to address 0x 6ff and in the waveform buffer, with address 0x800 to address 0xfff. spi b urst read is not available on other register add resses. a spi b urst r ead operation occur s for the options in table 25 where the n ext address is written. to enable burst read functionality on the registers from address 0x 5 00 to address 0x 6ff , set the burst_en bit in the config1 register to 1 . the waveform buffer burst read functionality is enabled by default and is managed by burst_chan in the wfb_cfg register. if these bits are set to 1111b, the burst read functionality of the waveform buffer is disabled. for further details on the burst read operation of waveform buffer contents, see the burst read waveform buffer samples f rom spi section . a burst read operation using the spi interface of the ade9078 is initiated when the ss pin goes low an d the ade9078 receives a 16- bit command header (cmd_hdr), with cmd_hdr , bit 3 = 1 that meet s the criteria in table 25 where the n ext address is written. following the command header, the ade9078 sends the register data for the register address ed i n the command . after the last bit of the first register value is received, the ade9078 auto - increment s the address and start s clocking out the data from the next registe r addres s . this process continu es until the master sets the ss line high . if the starting address is in the range of address 0x500 to address 0x516 and the spi is clocked beyond address 0x516 , the address is auto - incremen ted until it reaches address 0x5ff and th en wraps back t o the initial address. if the initial address is in the address 0x600 to address 0x63c or address 0x680 to address 0x6bc range and the spi is clocked beyond address 0x63c or address 0x6bc , it wraps back to the initial address. note that certain reserved registers in the valid spi burst address range read s zero during burst read operation.
ade9078 data sheet rev. 0 | page 64 of 107 after the ss line is set high by master, the ade9078 stops driving miso and enables a 100 k weak pull-up. it is recommended to have the sclk line idle high. an example of a spi burst read operation is given in figure 97, when burst_en = 1. for other examples, see the burst read waveform buffer samples from spi section. spi protocol crc the ade9078 spi port calculates a 16-bit cyclic redundancy check (crc-16) of the data sent out on its mosi pin so that the integrity of the data received by the master can be checked. the crc of the data sent out on the mosi pin during the last register read is offered in a 16-bit register, crc_spi, and can be appended to the spi read data as part of the spi transaction. the crc_spi register value is appended to the 16-/32-bit data read from the register addressed in the cmd_hdr for the cases in table 25 where crc is written (see the spi read section for more information). the crc result can always be read from the crc_spi register directly. there is no crc checking as part of the spi write register protocol. to ensure the data integrity of the spi write operation, read the register back to verify that the value is written to the ade9078 correctly. crc algorithm the crc algorithm implemented within the ade9078 is based on the crc-16 ccitt algorithm. the data output on miso is introduced into a linear feedback shift register (lfsr) based generator one byte at a time, msb first without bit reversal, as shown in figure 101 and figure 102. the 16-bit result is written in the crc_spi register. + lfsr generator a 31 a 0 07 8 15 1623 miso 32-bit data 24 31 24 31 16 23 815 07 14331-080 figure 101. crc calculat ion of 32-bit spi data a 15 a 0 + lfsr generator 07 8 15 miso 16-bit dat a 15 870 14331-081 figure 102. crc calculat ion of 16-bit spi data b 0 lfsr fb g 0 g 1 g 2 g 15 1 g 3 b 2 b 15 a 31 , a 30 , ..., a 2 , a 1 , a 0 14331-082 figure 103. lfsr generator used for crc_spi calculation figure 103 shows how the lfsr works. the miso 32-bit data forms the [a 31 , a 30 , , a 0 ] bits used by the lfsr. bit a 0 is bit 31 of the first miso 32-bit data to enter the lfsr, whereas the last data to enter the lfsr, bit a 31 , corresponds to bit 0 transmitted on miso. the formulas that govern the lfsr are as follows: b i (0) = 1, where i = 0, 1, 2, , 15, the initial state of the bits that form the crc. bit b 0 is the lsb, and bit b 15 is the msb. g i , where i = 0, 1, 2, , 15 are the coefficients of the generating polynomial defined by the crc-16 ccitt algorithm as follows: g ( x ) = x 16 + x 12 + x 5 + 1 (1) g 0 = g 5 = g 12 = 1 (2) all other g i coefficients are equal to 0. fb ( j) = a j ? 1 xor b 15 ( j ? 1) (3) b 0 ( j) = fb ( j) and g 0 (4) b i (j) = fb ( j) and g i xor b i ? 1 ( j ? 1), i = 1, 2, 3, , 15 (5) equation 3, equation 4, and equation 5 must be repeated for j = 1, 2, , 32. the value written into the crc_spi register contains bit b i (32), i = 0, 1, , 15. a similar process is followed for 16-bit data (see figure 102 for information about how the bits are ordered into the lfsr). additional communica tion verification registers the ade9078 includes three registers that allow spi operations to be verified. the last_cmd (address 0x04ae, last_ data_16 (address 0x4ac), and last_data_32 (address 0x423) registers record the received cmd_hdr and last read/transmitted data. the last_data_16 register contains the last data read or written during the last 16-bit transaction, whereas the last_data_32 holds the data read or written during the last 32-bit transaction. the last_cmd register is updated after the cmd_hdr is received. note that the three lsbs of last_cmd always reads back as 000. also note that if a command to read the last_cmd, last_data_16, or last_data_32 registers is received, these three registers are not updated. during a spi read operation, last_data_16 and last_data_32 are updated within two master clocks after the cmd_hdr is received.
data sheet ade9078 rev. 0 | page 65 of 107 note that the last_data_16 and last_data_32 registers are not updated after a spi b urst r ead operation these registers are the cases in table 25 where the next address is written. on a write ope ration, last_data_16 and last_data_32 are not updated until all 16 or 32 bits of the write data are recei ved . note that , on a write register operation, the addressed register is not written until all 16 or 32 bits are received, depending on the length of the register. note that w hen the last_ cmd , last_data_16 , and last_data_32 registers are read, their values remain unchanged. crc of configuration registers the con figuration register crc feature in the ade9078 monitors certain external and internal register values . it also optionally include s 1 2 registers that are individually selectable in the crc_opten register. see the crc_opten register in table 32 for more details. this feature runs as a background task it takes 10.8 ms to calculate the configuration register crc. the result is stored in the crc_rslt register. if any of the monitored r egisters change value , the crc_rslt register change s as well , and the crc_chg bit in the status 1 register is set , which can also be configured to generate an interrupt on irq1 . after configuring the ade9078 and writing the required registers to calibrate the measurements, such as xigain or xvgain, the configuration register crc calculation can be started by writing the force_crc_update bit in the crc_force register. when the calculation is complete, the crc_done bit is set in the status1 register. the method used for calculating the configuration register crc is also based on the crc - 16 ccitt algorithm. the most significan t b yte of each r egist er is introduced into the lfsr first, with out bit reversal ( see th e crc algorithm section for more information ) . the order in which the registers are calculated is given in table 26, with the lowest register introduced first. note that 32 - bit registe rs have four bytes introduced into the lfsr , whereas 16- bit register s have two bytes introduced in to the lfsr. note that the default value of certain internal registers can vary for each device and , thus, the default crc of configuration registers can vary for each device . table 26. order of registers i ncluded in the configuration register crc register addresses register length ( b its) 0x01 to 0x 1 8 32 0x21 to 0x 38 32 0x41 to 0x 58 32 0x60 to 0x 73 32 0x409 32 0x40f 32 0x420 to 0x 422 32 0x424 32 0x470 to 0x 475 32 0x480 to 0x 481 16 0x490 to 0x 497 16 0x499 16 0x4af to 0x 4b2 16 0x425 32 0x4b8 to 0x 4b9 16 0x47d 32 0x478 to 0x 479 32 0x4ef 16 0x4ba 16 0x47e 32 0x00 32 0x20 32 0x40 32 0x4b6 16 0x4bf 16 0x4b5 16 configuration lock the configuration lock featu r e prevents changes to the ade9078 configura tion. to enable this feature, wr ite 0x3c64 to the wr_lock register. to disable the feature, write 0x4ad1. to determine whether this feature is active, read the wr_lock register , w hich read s as 1 if the protection is enabled and 0 if it is disabled. when this feature is enabled, it prevents writing to a ddress 0x000 t o a ddress 0x0ff and a ddress 0x400 to a ddress 0x4ff.
ade9078 data sheet rev. 0 | page 66 of 107 waveform buffer the ade9078 has a waveform buffer comprised of 2048, 32-bit memory locations with addresses from address 0x800 to address 0xfff. this memory can be filled with samples from the sinc4 or sinc4 + iir lpf or current and voltage waveform samples processed by the digital signal processor. resampled waveforms make it easy to perform harmonic analysis in an external processor that can use the 16-bit, 64 points per line cycle samples directly in a fft, without having to perform any windowing functions. the data in the waveform buffer can come from four locations in the signal chain, as follows: ? sinc4 outputs, xi_sinc_dat, xv_sinc_dat: 16 ksps ? sinc4 + iir lpf output, xi_lpf_dat, xv_lpf_dat: 4 ksps ? current and voltage channel waveforms processed by the dsp (xi_pcf, xv_pcf): 4 ksps ? resampled waveforms with 64 points per line cycle processed by the dsp: data rate varies with line period figure 104 and figure 105 show the current and voltage channel datapaths, indicating which waveforms can be stored into the waveform buffer. filling and accessing of the waveform buffer depends on which type of data is being filled in the buffer. the waveforms with a fixed data rate, 16 ksps or 4 ksps, are referred to as fixed data rate waveforms. the following sections explain what modes/access are available for resampled waveforms versus fixed data rate waveforms. the waveform buffer samples can be accessed using the spi burst read functionality so that multiple samples can be read using only one spi command header (see the burst read waveform buffer samples from spi section). xigain hpf current peak detection reference - ? modulator ip v in v in +1v analog input range 0v ?1v ade9078 current channel (ia, ib, ic) sinc4 lpf 4:1 xigainx phase comp waveform buffer integrator wf_src wf_cap_sel mten hpfdis inten iconsel* ib = ?ia ? ic xi_pcf resampling adc_ redirect mux note: iconsel only affects ib channe l calculation total active and reactive power calcul ation zx_src_sel zx detection not available in ade9078 psm1 total current rms va power calcul ations fundamental reactive power calcul ations 14331-083 resampled waveform data range 0v 0v 0v 0xfbff_fb90 = ?67,110,000 0x0471_15c0 = +74,520,000 0x0474_e650 = +74,770,000 0v current channel (xi_pcf) data range sinc4 + iir lpf (xi_lpf_dat) data range sinc4 output (xi_sinc_dat) data range 0x0400_0470 = +67,110,000 0x46b4 = +18,100 0xb94c = ?18,100 0xfb8b_19b0 = ?74,770,000 0xfb8e_ea40 = ?74,520,000 16ksps 4ksps 4ksps figure 104. current channel datapath
data sheet ade9078 rev. 0 | page 67 of 107 14331-205 xvgain hpf voltage peak detection reference vp v in in +1v analog input range 0v ?1v ade9078 voltage channel sinc4 lpf 4:1 wf_src wf_cap_sel hpfdis total active and reactive power calculation zx_src_sel total voltage rms va power calculations fundamental reactive power calculations note: vconsel supports several 3-wire and 4-wire hardware configurations 100 va = va ? vb; vb = va ? vc; vc = vc ? vb; vb = ?va vb = ?va ? vc vb = va ? vc 011 010 001 000 resampled waveform range 0v 0v 0v 0xfbff_fb90 = ?67,110,000 0x0471_15c0 = +74,520,000 0x0474_e650 = +74,770,000 0v voltage channe l (xv_pcf) data range sinc4 + iir lpf (xv_lpf_dat) data range sinc4 output (xv_sinc_dat) data range 0x0400_0470 = +67,110,000 0x46b4 = +18,100 0xb94c = ?18,100 0xfb8b_19b0 = ?74,770,000 0xfb8e_ea40 = ?74,520,000 16 ksps 4 ksps waveform buffer resampling vconsel* 4 ksps not available in ade9078 psm1 figure 105. voltage channel datapath fixed data rate waveforms fixed data rate waveforms from the signal chain can be stored into the waveform buffer from the sources shown in table 27. table 27. fixed data rate waveform sources source wf_src data rate (ksps) 32-bit data format sinc4 outputs 0 16 according to figure 106 sinc4 + iir lpf output 2 4 according to figure 106 waveforms processed by the dsp (xi_pcf, xv_pcf) 3 4 5.27 format the 24-bit sinc4 and sinc4 + iir lpf data is stored as 32 bits in the waveform buffer by shifting left by 4 bits and sign extended. adc_data[23:0] 0000 se 14331-206 figure 106. format for the adc data stored in the waveform buffer, x_sinc_dat, and x_lpf_dat registers table 27 indicates the wf_src selection for each fixed data rate waveform source. each fixed data rate sample is 32-bit; however, the data format varies between the three sources, as indicated in table 27. when the waveform buffer is enabled, the data from all seven channels is stored into the buffer. one sample set consists of one sample per channel, seven samples total, which are taken at the same point in time. figure 107 shows how the fixed data rate samples are stored into the buffer. every sample set is separated in memory from the adjacent one by the use of spare cells, which do not contain any sample data, as shown in figure 107. in this way, every eighth 32-bit memory location in the buffer is reserved as a spare cell. if the seventh channel is disabled, with the wf_in_en bit in the wfb_cfg register = 0, the in sample locations are treated as spare cells as well. 0 xfff 0 31 in, if wfb_cfg.wf_in_en = 1 spare cell, if wfb_cfg.wf_in_en = 0 spare cell in 0x807 0x806 0x805 0x804 0x803 0x802 0x801 0x800 vc ic in vc ic vb ib va ia 14331-086 figure 107. fixed data rate waveform sample storage
ade9078 data sheet rev. 0 | page 68 of 107 there are 256 (2048/8) sample sets that can be stored in the buffer. in the ade9078 , the sinc4 outputs at 16 ksps so the buffer can contain (256/16,000) = 16 ms of data from the sinc4 filter. the sinc4 + iir lpf samples and dsp processed xi_pcf and xv_pcf waveform samples are filled at 4 khz, and the buffer can contain 64 ms (256/4000) of this data. when used with fixed data rate samples, the waveform buffer is divided into 16 pages, page 0 to page 15. each page contains 128 32-bit memory locations. figure 108 illustrates this arrangement. page 15 0x800 0x880 0x87f 0x900 0x8ff 0x980 0x97f 0x9ff 0xfff 0xf80 0xf7f 0xf00 0xeff page 14 pag e 3 pag e 2 pag e 1 pag e 0 14331-087 figure 108. waveform buffer page arrangementfor fixed data rate samples only waveform buffer filling indi cationfixed data rate samples the wfb_pg_irqen register allows the user to monitor if specific pages are filled, with one bit available per page. for example, if bit 0 and bit 3 of wfb_pg_irqen is set, the user receives an indication when address 0x87f has been written, when page 0 is full, and when address 0x9ff has been written, meaning that page 3 is full. the page_full bit of the status0 register is set to 1 when a page enabled in the wfb_pg_irqen register is filled. the user can enable an interrupt to occur on irq0 when the page_full bit is set by setting the page_full bit in the status0 register. the wfb_last_page bits in the wfb_trg_stat register indicate which page was filled last when filling with fixed data rate samples. fixed data rate waveforms filling and trigger-based modes the waveform buffer offers the following different filling modes to be used with fixed data rate samples: ? stop when buffer is full ? continuous filling the ade9078 allows a selection of events to trigger waveform buffer captures and there is an option to store the current waveform buffer address during an event to allow the user to synchronize the event with the waveform samples. the following waveform buffer actions can be associated with an event when the buffer is filling continuously: ? stop filling on trigger ? center capture around trigger ? save the event address and keep filling stop when buffer is full mode the stop when buffer is full mode is enabled when wf_cap_ sel = 1 and the wf_mode bits = 0 in the wfb_cfg register. set the wf_cap_en bit in the wfb_cfg register to start filling the buffer from address 0x800. after address 0xfff in page 15 is written, the filling operation stops. to receive an indication when the buffer is full, set bit 15 of the wfb_pg_irqen register prior to starting the capture. then, the page_full bit in status0 is set when the buffer is full. this page_full status change can be enabled to generate an interrupt on irq0 as well. to perform the next filling operation, disable the waveform buffer by clearing bit wf_cap_en of the wfb_cfg register to 0, and enable it again by setting the same bit to 1. continuous fill mode continuous fill mode is enabled when wf_cap_sel = 1 and wf_mode in the wfb_cfg register is equal to 1, 2, or 3. write the wf_cap_en bit in the wfb_cfg register to start filling the buffer from address 0x800. in this mode, the waveform buffer is filled continuously. after the entire buffer is filled up to address 0xfff, the filling continues from address 0x800 in a circular fashion. in this mode, it is important to monitor the filling status of the buffer using wfb_pg_irqen register in conjunction with the page_full bit in the status0 register and wfb_last_page bits in the wfb_trg_stat register, as described in the waveform buffer filling indicationfixed data rate samples section. if the data is not read out of the buffer soon enough, it is overwritten. to restart the filling operation, disable the waveform buffer by clearing the wf_cap_en bit of the wfb_cfg register, and then enable it again by setting this bit. it is recommended to read the wfb_last_page register before stopping the waveform buffer capture by clearing wf_cap_en so that the page that contains the most recent valid data is known. there are two variations on the continuous fill mode that stop filling the waveform buffer based on a trigger event: stop filling on trigger and center capture around trigger modes. these modes are selected when wf_mode = 1 and 2, respectively (see the stop filling on trigger and center capture around trigger sections for more information).
data sheet ade9078 rev. 0 | page 69 of 107 stop filling on trigger when wf_cap_sel = 1 and wf_mode = 1, stop filling on trigger mode is selected. it is recommended to use this mode to analyze the adc sa mples leading up to an event of interest . in this mode, the waveform buffer is filled continuously. after the entire buffer is filled up to a ddress 0xfff, the filling continues from a ddress 0x800 in a circular fashion. the events listed in table 28 are classified as trigger events. upon receiving a n enabled trigger event , the ade9078 stop s filling the waveform buffer. the events listed in table 28 can be enab led as waveform buffer triggers in the wfb_trg_cfg register. table 28. waveform buffer trigger e vents in the wfb_trg_cfg r egister bit (s) bit name comment 10 trig_force s et this bit to trigger an event to stop the waveform buffer fill ing 9 zxcomb z x on combined signal from va, vb, vc 8 zxvc zx event in p hase c voltage 7 zxvb zx event in p hase b voltage 6 zxva zx event in p hase a voltage 5 zxic zx event in p hase c current 4 zxib zx event in phase b current 3 zxia zx event in phase a current [ 2 : 0 ] reserved reserved the trigger events in the wfb_trg_cfg register , bits[10:3] correspond to interrupt events within the ade9078 with the exception of the trig_force bit. the user can set the trig_force bit, bit 10 in the wfb_trg_cfg register, to stop the filling the waveform buffer in this mode. when one of the events configured in wfb_trg_cfg occurs, the wfb_trig bit is set in the status0 register. this bit can be configured to generate an interrupt on the irq0 pin. after t he filling of the buffer stop s, the w fb_trg_irq bit is set in the status0 register. wfb_trg_irq can also be configured to generate an interrupt on the irq0 pin. at this time, the address of the in waveform of the last sample set is stored in the wfb_trig_addr bits of the wfb_trg_stat register. because the filling stops wh en the event occurs, any sample sets with addresses greater than the wfb_trig_addr register contain old data. to ensure that a buffers worth of samples are captured before the event, follow this sequence: 1. select stop capture on trigger mode by setting wf_cap_sel = 1 and wf_mode = 1 . 2. disable all trigger events by writing wfb_trg_cfg = 0 . 3. en sure that the buffer is filled one time by enabling an interrupt to oc cur on irq0 when the last page is filled by setting only bit 15 in the wfb_p g _irqen register and enabling the page_full bit in the status0 register. alternatively, read the last_page register instead of using the interrupt. 4. start the capt ure by writing wf_cap_en = 1 . 5. wait for the buffer to be filled , indicated by when the page_full interrupt occurs or last_page = 15. 6. then , enable the desired waveform buffer events in the wfb_trg_cfg register and set the wfb_trig_irq bit in status0 to gener ate an interrupt when the event has occurred and the waveform buffer has stopped filling. 7. when the wfb_trig_irq occurs, read wfb_trig_addr to see the address of the trigger event , which is within a sample or two of w hen the event occurred and is the last filled address. w aveform buffer values are retained when the w aveform buffer is disabled by clearing wf _cap_en in the wfb_cfg register ; however wfb_ l a st_ pa ge and wfb_trig_addr are reset when that bit is cleared. read the wfb_ last_page and wfb_trig_ addr bits before writing wf_cap_en = 0. trigger events given in table 28 must be enabled or disabled before enabling the waveform buffer by writing to the wfb_trg_cfg register. to perform the next filling operation in the s top f illing on t rigger mode, disable the waveform buffer by clearing the wf_cap_ en bit of the wfb_cfg and then enable it again by setting the sa me bit to 1 . note that if the trig_force bit was set to force a trigger that it must be cleared in the wfb_trg_cfg register before starting the next capture ( before writing wf_cap_en = 1 ) . center c apture a round t rigger the center capture around trigger mode is enabled when wf_cap_sel = 1 and wf_mode = 2 and is similar to the stop on trigger, except that the waveform buffer does not stop filling after the trigger event. even after the occurrence of the trigger event, the filling of the buffer continues to occur for the next 1024 32 - bit memory locations before stopping. it is recommended to use this mode to analyze samples before and after an event. see the stop filling on trigger section for more information about trigger events. note that in the center trigger mode, the wfb_trig bit in status0 is set when the enabled trigger event occurs while the w fb_trg_irq bit in status0 is s et when the 1024 additional memory locations are filled and the waveform buffer filling stops. both of these status bits can be configured to generate an interrupt on the irq0 pin. calculate the last filled address, using wfb_trig_addr , as follows : l ast filled address = wfb_trig_addr ? 1024 w here wfb_trig_addr +1024 > 0xfff. last filled address = wfb_trig_addr + 1024 where wfb_trig_addr + 1024 0xfff .
ade9078 data sheet rev. 0 | page 70 of 107 to ensure that a buffers worth of samples is captured before the event, follow this sequence: 1. select center capture on trigger mode by setting wf_cap_sel = 1 and wf_mode = 2. 2. disable all trigger events by writing wfb_trg_cfg = 0. 3. ensure that at least half of the buffer is filled by enabling an interrupt to occur on irq0 when the page 7 is filled by setting only bit 7 in the wfb_pg_irqen register and enabling the page_full bit in the status0 register. alternatively, read the wfb_last_page register instead of using the interrupt. 4. start the capture by writing wf_cap_en = 1. 5. wait for the buffer to be filled, which is indicated by the page_full interrupt occurring or wfb_last_page = 15. 6. enable the desired waveform buffer events in the wfb_ trg_cfg register and set the wfb_trig_irq bit in the status0 register to generate an interrupt when the event has occurred and the waveform buffer has stopped filling. 7. when the wfb_trig_irq occurs, read the wfb_trig_ addr register to acquire the address of the trigger event that is within a sample or two of when the event occurred. the last filled address is 1024 samples later. save event address and keep filling to record the waveform buffer address when a trigger event occurs while still filling the buffer, select wf_mode = 3 for continuous filling. when a trigger event that is enabled in the wfb_trg_cfg register occurs, the wfb_trig bit in the status0 register is set. wfb_trig can be configured to generate an interrupt on the irq0 pin. read the wfb_trig_ addr bits in the wfb_trig_stat register to acquire the waveform buffer address for the event. only the first enabled trigger address is stored; any later trigger events are ignored. resampled waveforms when resampling is enabled, the data from all seven channels is calculated and stored into the buffer. one sample set consists of one sample per channel, seven samples total, which are from the same point in time. each resampled waveforms sample is 16 bits. figure 109 shows how the resampled waveforms are stored into the buffer. every sample set is separated in memory from the adjacent one by the use of spare cells, as shown in figure 109. these spare cells do not contain any sample data. there is one 16-bit spare cell at the end of every fourth consecutive 32-bit memory location. if the neutral current channel is disabled, the 16-bit location that stores in samples also act as spare cells. in, if wf_in_en = 1 sparecell, if wf_in_en = 0 spare cell 0 15 31 0 xfff 0x802 0x801 0x800 in vc vb va ic ib ia in vc vb va ic ib ia in vc vb va ic ib ia 14331-088 figure 109. resampled waveform sample storage the waveform buffer contains 2048 32-bit memory locations and can hold 512 (2048/4) sets of samples in coherent fill mode. in the ade9078 , the buffer is filled with 64 points per line cycle, which implies that the buffer can hold eight line cycles worth of data at any instant in time. with a 50 hz line frequency, the buffer contains 160 ms worth of resampled data. first, to disable the waveform buffer, clear the wf_cap_en bit. then, clear the wf_cap_sel bit in the wfb_cfg register to select resampled data to be stored in the waveform buffer. finally, set the wf_cap_en bit to start the resampling process. the waveform buffer starts filling from its first address location, address 0x800. when the waveform buffer is full, the coh_ wfb_full bit of status0 goes high, which can be enabled to generate an interrupt on irq0 . note that this bit is the only status bit available for the resampled waveforms. the time taken to fill the buffer depends on the line frequency. the waveform buffer values are retained even when the waveform buffer is disabled, by clearing the wf_cap_en bit in the wfb_cfg register. to receive a new set of resampled data, disable the waveform buffer by resetting the wf_cap_en bit of the wfb_cfg register to 0, and enable it again by setting the same bit to 1. configuring the waveform buffer the waveform source, type of capture (fixed data rate or resampled), and fill mode (continuous, one time, or based on trigger) must be configured in the wfb_cfg register. to do so, first disable the waveform buffer by writing wf_cap_en = 0. then, write the wf_src, wf_cap_sel, and wf_mode bits of the wfb_cfg register.
data sheet ade9078 rev. 0 | page 71 of 107 when the wf_cap_en bit is set, whichever mode selected by the wf_cap_sel and wf_mode bits in the wfb_cfg register is initiated. for example, if wf_cap_sel = 0, the resampled waveforms are stored into the buffer. if wf_cap_sel = 1, the fixed data rate samples are stored into the buffer, and the wf_mode bits indicate whether the buffer is filled continuously or only one time, and if trigger events affects the buffer filling. all of these bits must be configured before writing the wf_cap_en bit in the wfb_cfg register. when the waveform buffer is disabled by clearing the wf_cap_en bit, the waveform buffer data remains valid; however, the wfb_last_addr and wfb_trig_addr registers are reset. to start a new waveform capture, disable the waveform buffer by writing wf_cap_en = 0. then, configure the wf_cap_sel and wf_mode bits as desired by writing to the wfb_cfg register. finally, set the wf_cap_en bit in the wfb_cfg register to start the capture. do not change the wf_cap_sel or wf_mode bits while the wf_cap_en bit is set. burst read waveform buffer samples from spi the waveform buffer contents can be read using the spi burst read mode. the spi burst read mode allows many samples of data to be read while only sending one spi command header. to make it easier to read out the desired data using the spi burst read functionality, the user can indicate which channels of data to read out of the waveform buffer, using the burst_chan bits in the wfb_cfg register, as shown in table 29. table 29. waveform buffer burst read burst_chan channels to burst 0000 (default) all channels 0001 ia and va 0010 ib and vb 0011 ic and vc 1000 ia 1001 va 1010 ib 1011 vb 1100 ic 1101 vc 1110 in if wf_in_en = 1 in the wfb_cfg register 1111 single address read (spi burst mode is disabled) the same burst_chan options are available for both fixed data rate samples and resampled data. the waveform buffer sample that is read out depends on the selection in burst_chan and whether the stored data is fixed data rate data or resampled data. if burst_chan is not equal to 1111, and the fixed data rate data is stored in the waveform buffer, when wf_cap_sel = 1, the three lsbs of the address are masked out when determining which sample set to read out. if burst_chan is not equal to 1111, and resampled data is stored in the waveform buffer, when wf_cap_sel = 0, the two lsbs of the address are masked out when determining which sample set to read out. if burst_chan = 1111, whichever address was written in the cmd_hdr is read out. these cases are summarized in table 30. table 30. spi address interpretation when reading from waveform buffer address of sample (set) capture type burst_chan 1111 burst_chan = 1111 fixed data rate samples (wf_cap_sel = 1) addr, bits[11:3] addr, bits [11:0] resampled data (wf_cap_sel = 0) addr, bits [11:2] addr, bits [11:0] example 1: fixed data ra te data, seven channel samples in this example, wfb_cap_sel = 1, wf_in_en = 1, and burst_chan = 0000 in the wfb_cfg register, which indicates that there is fixed data rate data in the waveform buffer, and the user wants to read out samples from all seven channels. a command is sent to read address 0x801, which is interpreted as a read to the sample set starting at address 0x800. the first 32 spi clocks return ia from address 0x800, followed by va from address 0x801, and so on until in returns from address 0x806. then, the sample set auto-increments and the next data is ia from address 0x808, followed by va. this example is depicted in figure 110. example 2: resampled data, phase c (i and v samples) in this example, wfb_cap_sel = 0 and burst_chan = 0011 in the wfb_cfg register, which indicates that there is resampled data in the waveform buffer, and the user wants to read out ic and vc samples. a command is sent to read address 0x801, which is interpreted as a read to the sample set starting at address 0x800. the first 16 spi clocks return the ic waveform from address 0x802, followed by vc from address 0x802. then, the sample set auto-increments and the next data is ic from address 0x806, followed by vc from the same address. then, ic from address 0x80a and vc from address 0x80a and are read out. this example is depicted in figure 111.
ade9078 data sheet rev. 0 | page 72 of 107 example 3: fixed data rate data, single address read mode in this example, wfb_cap_sel = 1 and burst_chan = 1111 in the wfb_cfg register, which indicates that there is fixed data rate data in the waveform buffer , and the user w ants to read out one single address. a command is sent to read address 0x801, which is interpreted as a read to address 0x801. th e first 32 spi clocks return the va waveform from address 0x801 , fol lowed by crc if burst_en = 0. if burst_en = 1, the va waveform data from a ddress 0x801 is repeated again. this example is depicted in figure 112 . exam ple 4: resampled data, single address read mode in this example, wfb_cap_sel = 0 and burst_chan = 1111 in the wfb_cfg register, which indicates that there is res ampled data in the waveform buffer , and the user w ants to read out one a single address. a command is sent to read address 0x801, which is interpreted as a read to a ddress 0x801. the first 16 spi clocks return the va waveform from a ddress 0x801, followed by the ia waveform from a ddress 0x801 , and , finally , the crc if burst_en = 0. if burst_en = 1, the va and ia waveform data from a ddress 0x801 is repeated again . this example is depicted in figure 113. sclk mosi cmd_hdr = 0x8018 miso i a a t 0x800, 32 bits ss i a a t 0x808, 32 bits v a a t 0x801, 32 bits ib a t 0x802,32 bits vb a t 0x803, 32 bits in a t 0x806, 32 bits 14331-089 figure 110 . waveform buffer spi burst read of fixed data rate samples, with burst_ch an = 0000 , to re ad out a ll channels (t he default s tate of the mosi p in d epends on the master spi d evice ; i t i s a ssumed to b e h igh (logic 1)) sclk mosi miso ss cmd_hdr = 0x8018 ic a t 0x802, 16 bits vc a t 0x802, 16 bits ic a t 0x806, 16 bits vc a t 0x806, 16 bits ic a t 0x80a, 16 bits 14331-090 111 0011 sclk mosi miso miso ss cmd_hdr = 0x8018 va at 0x801, 32 bits 3 1 crc, 16 bits 0 15 0 15 0 31 0 3 1 0 burst_en = 0 address 0x800 t o 0xfff burst_chan = 111 1 burst_en = 1 address 0x800 t o 0xfff burst_chan = 111 1 va at 0x801, 32 bits va at 0x801, 32 bits 14331-091 112 11 11
data sheet ade9078 rev. 0 | page 73 of 107 sclk mosi miso miso ss cmd_hdr = 0x8018 v a a t 0x801 crc, 16 bits 0 0 15 0 burst_en = 0 address 0x800 t o 0xfff burst_chan = 111 1 burst_en = 1 address 0x800 t o 0xfff burst_chan = 111 1 15 0 i a a t 0x801 15 15 15 v a a t 0x801 0 15 0 i a a t 0x801 v a a t 0x801 15 0 i a a t 0x801 15 14331-092 figure 113 . waveform buffer spi single address read of resampled data with burst_chan = 1111 spi crc w hen reading the waveform buffer when reading fixed data rate samples with wf_cap_sel = 1, data read o ut of the waveform buffer has a crc calculated , which is stored into the crc_spi register and can be read back after the waveform buffer burst read. when reading a single address of waveform buffer data, the crc_spi is calculated and appended after the 32 - bit data, as shown in figure 112. note that when reading resampled data out of the waveform buffer, when wf_cap_sel = 0, the crc _rslt register is not updated. it is recommended to read the waveform buffer a second time to check the integrity of the spi read data. spi last data register w hen reading the waveform buffer if burst_chan = 1111, the last_data_32 register is updated after reading a sample in the waveform buffer. n ote that t he last_data_32 register i s not updated when reading the waveform buffer samples if burst_chan is not equal to 1111.
ade9078 data sheet rev. 0 | page 74 of 107 interrupts/events the ade9078 has three pins ( irq0 , irq1 , and cf4/ event / dready) that can be used as interrupts to the host processor. the irq0 and irq1 pins go low when an enabled interrupt occurs and stay low until the event is acknowledged by setting the corresponding status bit in the status0 and status1 registers, respectively. the event function, which is multiplexed with the cf4 and dready options on the cf4/ event / dready pin, tracks the state of the enabled signals and goes low and high with these internal signals. the event function is especially useful for measuring the duration of events, such as no load, externally. interrupts ( irq0 and irq1 ) the irq0 and irq1 pins are managed by 32-bit interrupt mask registers, mask0 and mask1, respectively. every event that can generate an interrupt has a corresponding bit in the mask0 or mask1 register and status0 or status1 register. to enable an interrupt, set the corresponding bit in the mask0 or mask1 register. to disable an interrupt, the corresponding bit in mask0 or mask1 must be cleared. the status0 and status1 registers indicate if an event that can generate an interrupt has occurred. if the corresponding bit in the mask0 or mask1 register is set, an interrupt is generated on the corresponding irq0 or irq1 pin, and the pin goes low. to determine the source of the interrupt, read the corresponding status0 or status1 register and identify which enabled bits are set to 1. to acknowledge the event and clear bits in the statusx register, write to the statusx register with the desired bit positions set to 1. then, the corresponding irq0 or irq1 pin goes high. for example, if a zero crossing occurs on the phase a voltage input and the zxva bit is set in the mask1 register, the irq1 pin goes low, indicating that an enabled event has occurred. to acknowledge the event, write a 1 to the zxva bit in the status1 register and then the irq1 goes high. the zxva bit in the status1 register is set regardless of whether the zxva bit is enabled in the mask1 register. there are a few interrupts that are nonmaskable, meaning that they are generated even if the corresponding bit in the maskx register is 0. these nonmaskable interrupts include rstdone and error0. there is an option to combine all the interrupts onto a single interrupt pin, irq1 , instead of using two pins, irq0 and irq1 . to activate this option, set the irq0_on_irq1 bit in the config1 register. when irq0_on_irq1 = 1, irq1 indicates both irq0 and irq1 events, and irq0 indicates irq0 events. event the event function is multiplexed with cf4 and dready on the cf4/ event /dready pin. to enable the event function to be output on this pin, write cf4_cfg = 10 in the config1 register. the event_mask register manages which signals are incorporated into the event pin. all of these events sources are maskable and disabled by default. events are enabled by setting the corresponding mask bit to 1 in the event_mask register. the event pin goes low whenever one of the enabled events occurs and stay lows until all the enabled signals go high. then, the event pin goes high. the logic level of the event output is solely dependent on the enabled events; it cannot be changed by the user. note that the status sources that generate the event signal are not latchedif one event source is selected, the event pin tracks the status of that source. status bits in additional registers several interrupts are used in conjunction with other status registers. no load the rfnoload, vanload, and anload bits in the mask1 register function in conjunction with additional status bits in the phnoload register. the following bits in the mask0 register work with the status bits in the phsign register: revapx, revrpx, and revpsumx see table 32 for more information when the corresponding bits are set in the statusx register.
data sheet ade9078 rev. 0 | page 75 of 107 troubleshooting spi does not w ork c heck the pm x pins to ensure that pm0 and pm1 are set for the correct power mode (see the power mode s section ) . psm2_cfg register v alue i s n ot r etained w hen g oing fro m psm2 or psm3 to ps m0 this response is expected. psm2_cfg must be rewritten after entering psm0 or psm1 (see the power mode s section ) .
ade9078 data sheet rev. 0 | page 76 of 107 register i nformation table 31 . register summary addr . name description len ( b its) reset access 0x000 aigain phase a current gain adjust. 32 0x00000000 r/w 0x001 aigain0 phase a multipoint gain correction factor. if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, an additional gain factor, aigain0 through ai gain4 , is applied based on the airms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x002 aigain1 phase a multipoint gain correction facto r . if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, an additional gain factor, aigain0 through ai gain4 , is applied based on the airms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x003 aigain2 phase a multipoint gain correction factor . if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, an additional gain factor, aigain0 through ai gain4 , is applied based on the airms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x004 aigain3 phase a multipoint gain correction factor . if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, an additional gain factor, aigain0 through ai gain4 , is applied based on the airms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x005 aigain4 phase a multipoint gain correction factor . if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, an additional gain factor, aigain0 through ai gain4 , is applied based on the airms current rms amplitude and the mtthr_lx and mtthr_hx register v alues. 32 0x00000000 r/w 0x006 aphcal0 phase a multipoint phase correction factor. if multipoint phase and gain calibration is disabled, with mten = 0 in the config0 register, the aphcal0 phase compensation is applied. if multipoint phase and gain correction is enabled, with mten = 1, the aphcal0 through aphcal4 value is applied based on the airms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x007 aphcal1 phase a m ultipoint phase correction factor . if multipoint phase and gain calibration is disabled, with mten = 0 in the config0 register, the aphcal0 phase compensation is applied. if multipoint phase and gain correction is enabled, with mten = 1, thn the aphcal0 through aphcal4 value is applied based o n the airms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x008 aphcal2 phase a multipoint phase correction factor . if multipoint phase and gain calibration is disabled, with mten = 0 in the config0 register, the aphcal0 phase compensation is applied. if multipoint phase and gain correction is enabled, with mten = 1, the aphcal0 through aphcal4 value is applied based on the airms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x009 aphcal3 phase a multipoint phase correction factor . if multipoint phase and gain calibration is disabled, with mten = 0 in the config0 register, the aphcal0 phase compensation is applied. if multipoint phase and gain correction is enabled, with mten = 1, the aphcal0 through aphcal4 value is applied based on the airms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w
data sheet ade9078 rev. 0 | page 77 of 107 addr . name description len ( b its) reset access 0x00a aphcal4 phase a multipoint phase correction factor . if multipoint phase and gain calibration is disabled, with mten = 0 in the config0 register, the aphcal0 phase compensation is applied. if multipoint phase and gain correction is enabled, with mten = 1, the aphcal0 through aphcal4 value is applied based on the airms current rms amplit ude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x00b avgain phase a voltage gain adjust. 32 0x00000000 r/w 0x00c airmsos phase a current rms offset for filter based airms calculation. 32 0x00000000 r/w 0x00d avrmsos phase a voltage rms offset for filter based avrms calculation. 32 0x00000000 r/w 0x00e apgain phase a power gain adjust for awatt, ava, avar , and afvar calculations. 32 0x00000000 r/w 0x00f awat tos phase a total active power offset correction for awatt calculation. 32 0x00000000 r/w 0x010 avaros phase a total reactive power offset correction for avar calculation. 32 0x00000000 r/w 0x012 afvaros phase a fundamental reactive power offset correction for afvar calculation. 32 0x00000000 r/w 0x020 bigain phase b current gain adjust. 32 0x00000000 r/w 0x021 bigain0 phase b multipoint gain correction factor. if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, an additional gain factor, bigain0 through bi gain4 , is applied based on the birms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x022 bigain1 phase b multipoint gain correction factor . if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, an additional gain factor, bigain0 through bi gain4 , is applied based on the birms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x023 bigain2 phase b multipoint gain correction facto . if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, an additional gain factor, bigain0 through bi gain4 , is applied based on the birms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x024 bigain3 phase b multipoint gain correction factor . if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, an additional gain factor, bigain0 through bi gain4 , is applied based on the birms current rms amplitude and the mtthr_lx and mtt hr_hx register values. 32 0x00000000 r/w 0x025 bigain4 phase b multipoint gain correction factor . if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, an additional gain factor, bigain0 through bi gain4 , is applied based on the birms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x026 bphcal0 phase b multipoint phase correction factor. if multipoint phase and gain calibration is disabled, with mten = 0 in the config0 register, the bphcal0 phase compensation is applied. if multipoint phase and gain correction is enabled, with mten = 1, the bphcal0 through bphcal4 value is applied based on the birms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x027 bphcal1 phase b multipoint phase correction factor . if multipoint phase and gain calibration is disabled, with mten = 0 in the config0 register, the bphcal0 phase compensation is applied. if multipoint phase and gain correction is enabled, with mten = 1, the bphcal0 through bphcal4 value is applied based on the birms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w
ade9078 data sheet rev. 0 | page 78 of 107 addr . name description len ( b its) reset access 0x028 bphcal2 phase b multipoint phase correction factor . if multipoint phase and gain calibration is disabled, with mten = 0 in the config0 register, the bphcal0 phase compensation is applied. if multipoint phase and gain correction is enabled, with mten = 1, the bphcal0 through bphcal4 value is applied based on the birms current r ms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x029 bphcal3 phase b multipoint phase correction factor . if multipoint phase and gain calibration is disabled, with mten = 0 in the config0 register, the bphcal0 phase compensation is applied. if multipoint phase and gain correction is enabled, with mten = 1, the bphcal0 through bphcal4 value is applied based on the birms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x02a bphcal4 phase b multipoint phase correction factor . if multipoint phase and gain calibration is disabled, with mten = 0 in the config0 register, the bphcal0 phase compensation is applied. if multipoint phase and gain correction is enabled, with mten = 1, t he bphcal0 through bphcal4 value is applied based on the birms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x02b bvgain phase b voltage gain adjust. 32 0x00000000 r/w 0x02c birmsos phase b current rms offset for birms calculation. 32 0x00000000 r/w 0x02d bvrmsos phase b voltage rms offset for bvrms calculation. 32 0x00000000 r/w 0x02e bpgain phase b power gain adjust for bwatt, bva, bvar , and bfvar calculations. 32 0x00000000 r/w 0x02f bwat tos phase b total active power offset correction for bwatt calculation. 32 0x00000000 r/w 0x030 bvaros phase b total reactive power offset correction for bvar calculation. 32 0x00000000 r/w 0x032 bfvaros phase b fundamental reactive power offset correction for bfvar calculation. 32 0x00000000 r/w 0x040 cigain phase c current gain adjust. 32 0x00000000 r/w 0x041 cigain0 phase c multipoint gain correction factor. if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, an additional gain factor, cigain0 through ci gain4 , is applied based on the cirms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x042 cigain1 phase c multipoint gain correction factor . if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, an additional gain factor, cigain0 through ci gain4 , is applied based on the cirms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x043 cigain2 phase c multipoint gain correction factor . if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, an additional gain factor, cigain0 through ci gain4 , is applied based on the cirms current rms amplitude and the mtthr_lx and mtthr_hx regis ter values. 32 0x00000000 r/w 0x044 cigain3 phase c multipoint gain correction factor . if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, an additional gain factor, cigain0 through ci gain4 , is applied based on the cirms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x045 cigain4 phase c multipoint gain correction factor . if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, an additional gain factor, cigain0 through ci gain4 , is applied based on the cirms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w
data sheet ade9078 rev. 0 | page 79 of 107 addr . name description len ( b its) reset access 0x046 cphcal0 phase c multipoint phase correction factor. if multipoint phase and gain calibration is disabled, with mten = 0 in the config0 register, the cphcal0 phase compensation is applied. if multipoint phase and gain correction is enabled, with mten = 1, the cphcal0 through cphcal4 value is applied, based on the cirms current rms ampli tude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x047 cphcal1 phase c multipoint phase correction factor . if multipoint phase and gain calibration is disabled, with mten = 0 in the config0 register, the cphcal0 phase compensation is applied. if multipoint phase and gain correction is enabled, with mten = 1, the cphcal0 through cphcal4 value is applied, based on the cirms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x048 cphcal2 phase c multipoint phase correction factor . if multipoint phase and gain calibration is disabled, with mten = 0 in the config0 register, the cphcal0 phase compensation is applied. if multipoint phase and gain correction is enabled, with mten = 1, the cphcal0 throu gh cphcal4 value is applied, based on the cirms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x049 cphcal3 phase c multipoint phase correction factor . if multipoint phase and gain calibration is disabled, with mten = 0 in the config0 register, the cphcal0 phase compensation is applied. if multipoint phase and gain correction is enabled, with mten = 1, the cphcal0 through cphcal4 value is applied, based on the cirms current rms amplitude and the mtthr_lx and mtth r_hx register values. 32 0x00000000 r/w 0x04a cphcal4 phase c multipoint phase correction factor . if multipoint phase and gain calibration is disabled, with mten = 0 in the config0 register, the cphcal0 phase compensation is applied. if multipoint phase and gain correction is enabled, with mten = 1, the cphcal0 through cphcal4 value is applied, based on the cirms current rms amplitude and the mtthr_lx and mtthr_hx register values. 32 0x00000000 r/w 0x04b cvgain phase c voltage gain adjust. 32 0x00000000 r/w 0x04c cirmsos phase c current rms offset for cirms calculation. 32 0x00000000 r/w 0x04d cvrmsos phase c voltage rms offset for cvrms calculation. 32 0x00000000 r/w 0x04e cpgain phase c power gain adjust for cwatt, cva, cvar , and cfvar calculations. 32 0x00000000 r/w 0x04f cwat tos phase c total active power offset correction for cwatt calculation. 32 0x00000000 r/w 0x050 cvaros phase c total reactive power offset correction for cvar calculation. 32 0x00000000 r/w 0x052 cfvaros phase c fundamental reactive power offset correction for cfvar calculation. 32 0x00000000 r/w 0x060 config0 configuration r egister 0. 32 0x00000000 r/w 0x061 mtthr_l0 multipoint p hase/ g ain t hreshold. if mten = 1 in the config0 register, the mtthr_lx and mtthr_hx registers set up the ranges in which to apply each set of corrections, allo wing for hysteresis . s ee the multipoint gain and phase calibration section fo r more information. 32 0x00000000 r/w 0x062 mtthr_l1 multipoint phase/gain threshold -- see mtthr_l0 for more information. 32 0x00000000 r/w 0x063 mtthr_l2 multipoint phase/gain threshold -- see mtthr_l0 for more information. 32 0x00000000 r/w 0x064 mtthr_l3 multipoint phase/gain threshold -- see mtthr_l0 for more information. 32 0x00000000 r/w 0x065 mtthr_l4 multipoint phase/gain threshold -- see mtthr_l0 for more information. 32 0x00000000 r/w 0x066 mtthr_h0 multipoint phase/gain threshold -- see mtthr_l0 for more information. 32 0x00000000 r/w 0x067 mtthr_h1 multipoint phase/gain threshold -- see mtthr_l0 for more information. 32 0x00000000 r/w 0x068 mtthr_h2 multipoint phase/gain threshold -- see mtthr_l0 for more information. 32 0x00000000 r/w 0x069 mtthr_h3 multipoint phase/gain threshold -- see mtthr_l0 for more information. 32 0x00000000 r/w
ade9078 data sheet rev. 0 | page 80 of 107 addr . name description len ( b its) reset access 0x06a mtthr_h4 multipoint phase/gain threshold -- see mtthr_l0 for more information. 32 0x00000000 r/w 0x06b nirmsos neutral current rms offset for nirms calculation. 32 0x00000000 r/w 0x06c isumrmsos offset correction for isumrms calculation based on the sum of ia + ib + ic in. 32 0x00000000 r/w 0x06d nigain neutral current gain adjust. 32 0x00000000 r/w 0x06e nphcal neutral current phase compensation. 32 0x00000000 r/w 0x071 vnom nominal phase voltage rms used in the computation of apparent power, xva, when vnomx_en bit is set in the config0 register. 32 0x00000000 r/w 0x072 dicoeff value used in the digital integrator algorithm. if the integrator is turned on, with inten or ininten equal to one in the config0 register, it is recommended to set this value to 0xffffe000. 32 0x00000000 r/w 0x073 isumlvl threshold to compare isumrms against. configure this register to receive a mismtch indication in status0 if isumrms exceeds this threshold. 32 0x00000000 r/w 0x20a ai_pcf instantaneous phase a c urrent c hannel w aveform processed by the dsp, at 4 ksps . 32 0x00000000 r 0x20b av_pcf instantaneous phase a voltage channel waveform processed by the dsp , at 4 ksps . 32 0x00000000 r 0x20c airms phase a f ilter based current rms value, updates at 4 ksps . 32 0x00000000 r 0x20d avrms phase a filter based v oltage rms value, updates at 4 ksps . 32 0x00000000 r 0x210 awat t phase a l ow - pass filtered total active power, updated at 4 ksps . 32 0x00000000 r 0x211 avar phase a l ow - pass filtered total reactive power, updated at 4 ksps . 32 0x00000000 r 0x212 ava phase a t otal apparent power, updated at 4 ksps . 32 0x00000000 r 0x214 afvar phase a f undamental reactive power, updated at 4 ksps . 32 0x00000000 r 0x216 apf phase a p ower f actor, updated at 1.024 s ec . 32 0x00000000 r 0x21d amtregion if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, these bits indicate which aigainx and aphcalx is currently being used. 32 0x0000000f r 0x22a bi_pcf instantaneous phase b current channel waveform processed by the dsp, at 4 ksps . 32 0x00000000 r 0x22b bv_pcf instantaneous phase b voltage channel waveform processed by the dsp, at 4 ksps . 32 0x00000000 r 0x22c birms phase b filter based current rms value, updates at 4 ksps . 32 0x00000000 r 0x22d bvrms phase b filter based voltage rms value, updates at 4 ksps . 32 0x00000000 r 0x230 bwat t phase b low - pass filtered total active power, updated at 4 ksps . 32 0x00000000 r 0x231 bvar phase b low - pass filtered total reactive power, updated at 4 ksps . 32 0x00000000 r 0x232 bva phase b t otal apparent power, updated at 4 ksps . 32 0x00000000 r 0x234 bfvar phase b fundamental reactive power, updated at 4 ksps . 32 0x00000000 r 0x236 bpf phase b p ower f actor, updated at 1.024 s ec . 32 0x00000000 r 0x23d bmtregion if multipoint gain and phase compensation is enabled, with mten = 1 in the cofig0 register, these bits indicate which bigainx and bphcalx is currently being used. 32 0x0000000f r 0x24a ci_pcf instantaneous phase c current channel waveform processed by the dsp, at 4 ksps . 32 0x00000000 r 0x24b cv_pcf instantaneous phase c voltage channel waveform processed by the dsp, at 4 ksps . 32 0x00000000 r 0x24c cirms phase c filter based current rms value, updates at 4 ksps . 32 0x00000000 r
data sheet ade9078 rev. 0 | page 81 of 107 addr . name description len ( b its) reset access 0x24d cvrms phase c filter based voltage rms value, updates at 4 ksps . 32 0x00000000 r 0x250 cwat t phase c l ow - pass filtered total active power, updated at 4 ksps . 32 0x00000000 r 0x251 cvar phase c l ow - pass filtered total reactive power, updated at 4 ksps . 32 0x00000000 r 0x252 cva phase c t otal apparent power, updated at 4 ksps . 32 0x00000000 r 0x254 cfvar phase c f undamental reactive power, updated at 4 ksps . 32 0x00000000 r 0x256 cpf phase c p ower f actor, updated at 1.024 s ec . 32 0x00000000 r 0x25d cmtregion if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, these bits indicate which cigainx and cphcalx is currently being used. 32 0x0000000f r 0x265 ni_pcf instantaneous n eutral c urrent c hannel w aveform processed by the dsp, at 4 ksps . 32 0x00000000 r 0x266 nirms neutral c urrent filter based rms value. 32 0x00000000 r 0x269 isumrms filter b ased rms based on the sum of ia + ib + ic in. 32 0x00000000 r 0x26a v ersion 2 this register indicates the version of the metrology algorithms after the user writes run = 1 to start the measurements. 32 0x0000000c r 0x2e5 awat t_acc phase a accumulated total active power, updated after pwr_time 4 ksps samples. 32 0x00000000 r 0x2e6 awat thr_lo phase a accumulated total active energy, lsb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x2e7 awatthr_hi phase a accumulated total active energy, msb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x2ef avar_acc phase a accumulated total reactive power, updated after pwr_time 4 ksps samples. 32 0x00000000 r 0x2f0 avarhr_lo phase a accumulated total reactive energy, lsb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x2f1 avarhr_hi phase a accumulated total reactive energy, msb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x2f9 ava_acc phase a accumulated total apparent power, updated after pwr_time 4 ksps samples. 32 0x00000000 r 0x2fa avahr_lo phase a accumulated total apparent energy, lsb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x2fb avahr_hi phase a accumulated total apparent energy, lsb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x30d afvar_acc phase a accumulated fundamental reactive power, updated after pwr_time 4 ksps samples. 32 0x00000000 r 0x30e afvarhr_lo phase a accumulated fundamental reactive energy, lsb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x30f afvarhr_hi phase a accumulated fundamental reactive energy, msb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x321 bwat t_acc phase b accumulated total active power, updated after pwr_time 4 ksps samples. 32 0x00000000 r 0x322 bwat thr_lo phase b accumulated total active energy, lsb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x323 bwatthr_hi phase b accumulated total active energy, msb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x32b bvar_acc phase b accumulated total reactive power, updated after pwr_time 4 ksps samples. 32 0x00000000 r
ade9078 data sheet rev. 0 | page 82 of 107 addr . name description len ( b its) reset access 0x32c bvarhr_lo phase b accumulated total reactive energy, lsb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x32d bvarhr_hi phase b accumulated total reactive energy, msb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x335 bva_acc phase b accumulated total apparent power, updated after pwr_time 4 ksps samples. 32 0x00000000 r 0x336 bvahr_lo phase b accumulated total apparent energy, lsb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x337 bvahr_hi phase b accumulated total apparent energy, msb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x349 bfvar_acc phase b accumulated fundamental reactive power, updated after pwr_time 4 ksps samples. 32 0x00000000 r 0x34a bfvarhr_lo phase b accumulated fundamental reactive energy, lsb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x34b bfvarhr_hi phase b accumulated fundamental reactive energy, msb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x35d cwat t_acc phase c accumulated total active power, updated after pwr_time 4 ksps samples. 32 0x00000000 r 0x35e cwat thr_lo phase c accumulated total active energy, lsb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x35f cwatthr_hi phase c accumulated total active energy, msb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x367 cvar_acc phase c accumulated total reactive power, updated after pwr_time 4 ksps samples. 32 0x00000000 r 0x368 cvarhr_lo phase c accumulated total reactive energy, lsb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x369 cvarhr_hi phase c accumulated total reactive energy, msb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x371 cva_acc phase c accumulated total apparent power, updated after pwr_time 4 ksps samples. 32 0x00000000 r 0x372 cvahr_lo phase c accumulated total apparent energy, lsb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x373 cvahr_hi phase c accumulated total apparent energy, msb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x385 cfvar_acc phase c accumulated fundamental reactive power, updated after pwr_time 4 ksps samples. 32 0x00000000 r 0x386 cfvarhr_lo phase c accumulated fundamental reactive energy, lsb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x387 cfvarhr_hi phase c accumulated fundamental reactive energy, msb s. updated according to the settings in ep_cfg and egy_time registers. 32 0x00000000 r 0x397 pwat t_acc accumulated positive total active power, msb s, from awatt, bwatt and cwatt registers, updated after pwr_time 4 ksps samples. 32 0x00000000 r 0x39b nwat t_acc accumulated negative total active power, msb s, from awatt, bwatt and cwatt registers, updated after pwr_time 4 ksps samples. 32 0x00000000 r 0x39f pvar_acc accumulated positive total reactive power, msb s, from avar, bvar and cvar registers, updated after pwr_time 4 ksps samples. 32 0x00000000 r 0x3a3 nvar_acc accumulated negative total reactive power, msb s, from avar, bvar and cvar registers, updated after pwr_time 4 ksps samples. 32 0x00000000 r 0x400 ipeak current peak register. 32 0x00000000 r
data sheet ade9078 rev. 0 | page 83 of 107 addr . name description len ( b its) reset access 0x401 vpeak voltage peak register. 32 0x00000000 r 0x402 status0 status register 0. 32 0x00000000 r/w 0x403 status1 status register 1. 32 0x00000000 r/w 0x404 event_status event status register. 32 0x00000000 r 0x405 mask0 interrupt enable register 0. 32 0x00000000 r/w 0x406 mask1 interrupt enable register 1. 32 0x00000000 r/w 0x407 event_mask event e nable r egister. 32 0x00000000 r/w 0x40e user_period user configured line period value used for resampling when the uperiod_sel bit in the config2 register is set. 32 0x00500000 r/w 0x40f vlevel register used in the algorithm that computes the fundamental reactive power. 32 0x00045d45 r/w 0x418 aperiod line period on phase a voltage. 32 0x00a00000 r 0x419 bperiod line period on phase b voltage. 32 0x00a00000 r 0x41a cperiod line period on phase c voltage. 32 0x00a00000 r 0x41b com_period line period measurement on combined signal from phase a, phase b, and phase c v oltages. 32 0x00a00000 r 0x41c act_nl_lvl no load threshold in the total active power datapath. 32 0x0000ffff r/w 0x41d react_nl_lvl no load threshold in the total and fundamental reactive power datapath. 32 0x0000ffff r/w 0x41e app_nl_lvl no load threshold in the total apparent power datapath. 32 0x0000ffff r/w 0x41f phnoload phase n o load register. 32 0x00000000 r 0x420 wthr sets the maximum output rate from the digital to frequency converter for the total active power for the cf calibration pulse output. it is recommended to write wthr = 0x0010 0000. 32 0x0000ffff r/w 0x421 varthr sets the maximum output rate from the digital to frequency converter for the total and fundamental reactive power for the cf calibration pulse output. it is recommended to write varthr = 0x0010 0000. 32 0x0000ffff r/w 0x422 vathr sets the maximum output rate from the digital to frequency converter for the total apparent power for the cf calibration pulse output. it is recommended to write vathr = 0x0010 0000. 32 0x0000ffff r/w 0x423 last_data_32 this register holds the data read or written during the last 32 - bit transaction on the spi port. 32 0x00000000 r 0x424 adc_redirect this register allows any adc output to be redirected to any digital datapath. 32 0x001fffff r/w 0x425 cf_lcfg cf calibration pulse width configuration register. 32 0x00000000 r/w 0x472 part_id this register identifies the ic. if the ade9000_id bit is 0, the ic is an ade9078 . 32 0x00000000 r 0x480 run write this register to 1 to start the measurements. 16 0x0000 r/w 0x481 config1 configuration r egister 1. 16 0x0000 r/w 0x482 angl_va_vb time between positive to negative zero crossings on phase a and phase b v oltages. 16 0x0000 r 0x483 angl_vb_vc time between positive to negative zero crossings on phase b and phase c voltages . 16 0x0000 r 0x484 angl_va_vc time between positive to negative zero crossings on phase a and phase c voltages . 16 0x0000 r 0x485 angl_va_ia time between positive to negative zero crossings on phase a voltage and c urrent. 16 0x0000 r 0x486 angl_vb_ib time between positive to negative zero crossings on phase b voltage and current. 16 0x0000 r
ade9078 data sheet rev. 0 | page 84 of 107 addr . name description len ( b its) reset access 0x487 angl_vc_ic time between positive to negative zero crossings on phase c voltage and current. 16 0x0000 r 0x488 angl_ia_ib time between positive to negative zero crossings on phase a and phase b current . 16 0x0000 r 0x489 angl_ib_ic time between positive to negative zero crossings on phase b and phase c current . 16 0x0000 r 0x48a angl_ia_ic time between positive to negative zero crossings on phase a and phase c current . 16 0x0000 r 0x490 cfmode cfx configuration register. 16 0x0000 r/w 0x491 compmode computation mode register. 16 0x0000 r/w 0x492 accmode accumulation mode register. 16 0x0000 r/w 0x493 config3 configuration r egister 3. 16 0x0000 r/w 0x494 cf1den cf1 denominator register. 16 0xffff r/w 0x495 cf2den cf2 denominator register. 16 0xffff r/w 0x496 cf3den cf3 denominator register. 16 0xffff r/w 0x497 cf4den cf4 denominator register. 16 0xffff r/w 0x498 zxtout zero - crossing timeout configuration register. 16 0xffff r/w 0x499 zxthrsh voltage c hannel z ero - crossing threshold register. 16 0x0009 r/w 0x49a zx_lp_sel this register selects which zero crossing and which line period measurement are used for other calculations. 16 0x001e r/w 0x49c seq_cyc number of line cycles used for phase sequence detection. it is recommended to set this register to 1. 16 0x00ff r/w 0x49d phsign power sign register. 16 0x0000 r 0x4a0 wfb_cfg waveform b uffer c onfiguration register. 16 0x0000 r/w 0x4a1 wfb_pg_irqen this register enables interrupts to occur after specific pages of the waveform buffer have been filled. 16 0x0000 r/w 0x4a2 wfb_trg_cfg this register enables events to trigger a capture in the waveform buffer. 16 0x0000 r/w 0x4a3 wfb_trg_stat this register indicates the last page that was filled in the waveform buffer and the location of trigger events. 16 0x0000 r/w 0x4a4 config5 configuration r egister 5. 16 0x0063 r/w 0x4a8 crc_rslt this register holds the crc of configuration registers. 16 0x0000 r 0x4a9 crc_spi this register holds the 16 - bit crc of the data sent out on the mosi pin during the last spi register read. 16 0x0000 r 0x4ac last_data_16 this register holds the data read or written during the last 16 - bit transaction on the spi port. 16 0x0000 r 0x4ae last_cmd this register holds the address and read/write operation request (cmd_hdr) for the last transaction on the spi port. 16 0x0000 r 0x4af config2 configuration r egister 2. 16 0x0c00 r/w 0x4b0 ep_cfg energy and power accumulation configuration. 16 0x0000 r/w 0x4b1 pwr_time power u pdate time configuration. 16 0x00ff r/w 0x4b2 egy_time energy accumulation update time configuration. 16 0x00ff r/w 0x4b4 crc_force this register forces an update of the crc of configuration registers. 16 0x0000 r/w 0x4b5 crc_opten this register selects which registers are optionally included in the configuration register crc feature. 16 0x0000 r/w
data sheet ade9078 rev. 0 | page 85 of 107 addr . name description len ( b its) reset access 0x4b8 psm2_cfg this register configures settings for the low power psm2 operating mode. this register value is retained in psm2 and psm3 but is rewritten to its default value when entering psm0 or psm1. 16 0x001f r/w 0x4b9 pga_gain this register configures the pga gain for each adc. 16 0x0000 r/w 0x4ba chnl_dis this register can be disable s the adcs individually. 16 0x0000 r/w 0x4bf wr_lock this register enables the configuration lock feature. 16 0x0000 r/w 0x4e0 var_dis enable/disable total reactive power calculation. 16 0x0000 r/w 0x4f0 reserved1 this register is reserved. 16 0x0000 r 0x4fe v ersion version of the ade9078 ic. 16 0x0040 r 0x500 ai_sinc_dat current c hannel a adc waveforms from sinc4 output, at 16 ksps . 32 0x00000000 r 0x501 av_sinc_dat voltage channel a adc waveforms from sinc4 output, at 16 ksps . 32 0x00000000 r 0x502 bi_sinc_dat current channel b adc waveforms from sinc4 output, at 16 ksps . 32 0x00000000 r 0x503 bv_sinc_dat voltage channel b adc waveforms from sinc4 output, at 16 ksps . 32 0x00000000 r 0x504 ci_sinc_dat current channel c adc waveforms from sinc4 output, at 16 ksps . 32 0x00000000 r 0x505 cv_sinc_dat voltage channel c adc waveforms from sinc4 output, at 16 ksps . 32 0x00000000 r 0x506 ni_sinc_dat neutral current channel adc waveforms from sinc4 output, at 16 ksps . 32 0x00000000 r 0x510 ai_lpf_dat current channel a adc waveforms from sinc4 + iir lpf and decimator output, at 4 ksps . 32 0x00000000 r 0x511 av_lpf_dat voltage channel a adc waveforms from sinc4 + iir lpf output, at 4 ksps . 32 0x00000000 r 0x512 bi_lpf_dat current channel b adc waveforms from sinc4 + iir lpf output, at 4 ksps . 32 0x00000000 r 0x513 bv_lpf_dat voltage channel b adc waveforms from sinc4 + iir lpf output, at 4 ksps . 32 0x00000000 r 0x514 ci_lpf_dat current channel c adc waveforms from sinc4 + iir lpf output, at 4 ksps . 32 0x00000000 r 0x515 cv_lpf_dat voltage channel c adc waveforms from sinc4 + iir lpf output, at 4 ksps . 32 0x00000000 r 0x516 ni_lpf_dat neutral current channel adc waveforms from sinc4 + iir lpf output, at 4 ksps . 32 0x00000000 r 0x600 av_pcf_1 spi b urst r ead a ccessible. registers organized functionally . see av_pcf in table 31. 32 0x00000000 r/w 0x601 bv_pcf_1 spi burst read accessible . registers organized functionally. see bv_pcf in table 31. 32 0x00000000 r/w 0x602 cv_pcf_1 spi burst read accessible . registers organized functionally. see cv_pcf in table 31. 32 0x00000000 r/w 0x603 ni_pcf_1 spi burst read accessible . registers organized functionally. see ni_pcf in table 31. 32 0x00000000 r/w 0x604 ai_pcf_1 spi burst read accessible . registers organized functionally. see ai_pcf in table 31. 32 0x00000000 r/w 0x605 bi_pcf_1 spi burst read accessible . registers organized functionally. see bi_pcf in table 31. 32 0x00000000 r/w 0x606 ci_pcf_1 spi burst read accessible . registers organized functionally. see ci_pcf in table 31. 32 0x00000000 r/w 0x607 airms_1 spi burst read accessible . registers organized functionally. see airms in table 31. 32 0x00000000 r/w 0x608 birms_1 spi burst read accessible . registers organized functionally. see birms in table 31. 32 0x00000000 r/w 0x609 cirms_1 spi burst read accessible . registers organized functionally. see cirms in table 31. 32 0x00000000 r/w
ade9078 data sheet rev. 0 | page 86 of 107 addr . name description len ( b its) reset access 0x60a avrms_1 spi burst read accessible . registers organized functionally. see avrms in table 31. 32 0x00000000 r/w 0x60b bvrms_1 spi burst read accessible . registers organized functionally. see bvrms in table 31. 32 0x00000000 r/w 0x60c cvrms_1 spi burst read accessible . registers organized functionally. see cvrms in table 31. 32 0x00000000 r/w 0x60d nirms_1 spi burst read accessible . registers organized functionally. see nirms in table 31. 32 0x00000000 r/w 0x60e awat t_1 spi burst read accessible . registers organized functionally. see awatt in table 31. 32 0x00000000 r/w 0x60f bwat t_1 spi burst read accessible . registers organized functionally. see bwatt in table 31. 32 0x00000000 r/w 0x610 cwat t_1 spi burst read accessible . registers organized functionally. see cwatt in table 31. 32 0x00000000 r/w 0x611 ava_1 spi burst read accessible . registers organized functionally. see ava in table 31. 32 0x00000000 r/w 0x612 bva_1 spi burst read accessible . registers organized functionally. see bva in table 31. 32 0x00000000 r/w 0x613 cva_1 spi burst read accessible . registers organized functionally. see cva in table 31. 32 0x00000000 r/w 0x614 avar_1 spi burst read accessible . registers organized functionally. see avar in table 31. 32 0x00000000 r/w 0x615 bvar_1 spi burst read accessible . registers organized functionally. see bvar in table 31. 32 0x00000000 r/w 0x616 cvar_1 spi burst read accessible . registers organized functionally. see cvar in table 31. 32 0x00000000 r/w 0x617 afvar_1 spi burst read accessible . registers organized functionally. see afvar in table 31. 32 0x00000000 r/w 0x618 bfvar_1 spi burst read accessible . registers organized functionally. see bfvar in table 31. 32 0x00000000 r/w 0x619 cfvar_1 spi burst read accessible . registers organized functionally. see cfvar in table 31. 32 0x00000000 r/w 0x61a apf_1 spi burst read accessible . registers organized functionally. see apf in table 31. 32 0x00000000 r/w 0x61b bpf_1 spi burst read accessible . registers organized functionally. see bpf in table 31. 32 0x00000000 r/w 0x61c cpf_1 spi burst read accessible . registers organized functionally. see cpf in table 31. 32 0x00000000 r/w 0x680 av_pcf_2 spi burst read accessible . registers organized by phase. see av_pcf in table 31. 32 0x00000000 r/w 0x681 ai_pcf_2 spi burst read accessible . registers organized by phase. see ai_pcf in table 31. 32 0x00000000 r/w 0x682 airms_2 spi burst read accessible . registers organized by phase. see airms in table 31. 32 0x00000000 r/w 0x683 avrms_2 spi burst read accessible . registers organized by phase. see avrms in table 31. 32 0x00000000 r/w 0x684 awat t_2 spi burst read accessible . registers organized by phase. see awatt in table 31. 32 0x00000000 r/w 0x685 ava_2 spi burst read accessible . registers organized by phase. see ava in table 31. 32 0x00000000 r/w
data sheet ade9078 rev. 0 | page 87 of 107 addr . name description len ( b its) reset access 0x686 avar_2 spi burst read accessible . registers organized by phase. see avar in table 31 . 32 0x00000000 r/w 0x687 afvar_2 spi burst read accessible . registers organized by phase. see afvar in table 31. 32 0x00000000 r/w 0x688 apf_2 spi burst read accessible . registers organized by phase. see apf in table 31 . 32 0x00000000 r/w 0x693 bv_pcf_2 spi burst read accessible . registers organized by phase. see bv_pcf in table 31. 32 0x00000000 r/w 0x694 bi_pcf_2 spi burst read accessible . registers organized by phase. see bi_pcf in table 31. 32 0x00000000 r/w 0x695 birms_2 spi burst read accessible . registers organized by phase. see birms in table 31. 32 0x00000000 r/w 0x696 bvrms_2 spi burst read accessible . registers organized by phase. see bvrms in table 31. 32 0x00000000 r/w 0x697 bwat t_2 spi burst read accessible . registers organized by phase. see bwatt in table 31. 32 0x00000000 r/w 0x698 bva_2 spi burst read accessible . registers organized by phase. see bva in table 31. 32 0x00000000 r/w 0x699 bvar_2 spi burst read accessible . registers organized by phase. see bvar in table 31. 32 0x00000000 r/w 0x69a bfvar_2 spi burst read accessible . registers organized by phase. see bfvar in table 31. 32 0x00000000 r/w 0x69b bpf_2 spi burst read accessible . registers organized by phase. see bpf in table 31. 32 0x00000000 r/w 0x6a6 cv_pcf_2 spi burst read accessible . registers organized by phase. see cv_pcf in table 31. 32 0x00000000 r/w 0x6a7 ci_pcf_2 spi burst read accessible . registers organized by phase. see ci_pcf in table 31. 32 0x00000000 r/w 0x6a8 cirms_2 spi burst read accessible . registers organized by phase. see cirms in table 31. 32 0x00000000 r/w 0x6a9 cvrms_2 spi burst read accessible . registers organized by phase. see cvrms in table 31. 32 0x00000000 r/w 0x6aa cwat t_2 spi burst read accessible . registers organized by phase. see cwatt in table 31. 32 0x00000000 r/w 0x6ab cva_2 spi burst read accessible . registers organized by phase. see cva in table 31. 32 0x00000000 r/w 0x6ac cvar_2 spi burst read accessible . registers organized by phase. see cvar in table 31. 32 0x00000000 r/w 0x6ad cfvar_2 spi burst read accessible . registers organized by phase. see cfvar in table 31. 32 0x00000000 r/w 0x6ae cpf_2 spi burst read accessible . registers organized by phase. see cpf in table 31. 32 0x00000000 r/w 0x6b9 ni_pcf_2 spi burst read accessible . registers organized by phase. see ni_pcf in table 31. 32 0x00000000 r/w 0x6ba nirms_2 spi burst read accessible . registers organized by phase. see nirms in table 31. 32 0x00000000 r/w
ade9078 data sheet rev. 0 | page 88 of 107 r egister d etails t able 32 . register details addr . name bits bit name settings description reset access 0x060 config0 [31:14] reserved reserved. 0x0 r 13 disrplpf set this bit to disable the low - pass filter in the total reactive power datapath . 0x0 r/w 12 disaplpf set this bit to disable the low - pass filter in the total active power datapath . 0x0 r/w 11 ininten set this bit to enable the digital integrator in the neutral current channel . 0x0 r/w 10 vnomc_en set this bit to use the nominal phase voltage rms, vnom, in the computation of phase c total apparent power, cva . 0x0 r/w 9 vnomb_en set this bit to use the nominal phase voltage rms, vnom, in the computation of phase b total apparent power, bva . 0x0 r/w 8 vnoma_en set this bit to use the nominal phase voltage rms, vnom, in the computation of phase a total apparent power, ava . 0x0 r/w 7 reserved reserved. 0x0 r 6 zx_src_sel this bit selects whether data going into the zero - crossing detection circuit comes before the high - pass filter, integrator , and phase compensation or afterwards . 0x0 r/w 0 after the high - pass filter, integrator , and phase compensation. 1 before the high - pass filter, integrator , and phase compensation. 5 inten set this bit to enable the integrators in the phase current channels. the neutral current channel integrator is managed by the ininten bit in the config0 register. 0x0 r/w 4 mten set this bit to enable multipoint phase and gain compensation. if enabled, an additional gain factor, xigain0 through xi gain4 , is applied to the current channel based on the xirms current rms amplitude and the mtthr_lx and mtthr_hx register values. 0x0 r/w 3 hpfdis set this bit to disable high - pass filters in all the voltage and current channels. 0x0 r/w 2 reserved reserved. 0x0 r [1:0] isum_cfg isum calculation configuration . 0x0 r/w 00 isum = ai_pcf + bi_pcf + ci_pcf (for approximated neutral current rms calculation) . 01 isum = ai_pcf + bi_pcf + ci_pcf + ni_pcf (to determine mismatch between neutral and phase currents) . 10 isum = ai_pcf + bi_pcf + ci_pcf - ni_pcf (to determine mismatch between neutral and phase currents) . 11 isum = ai_pcf + bi_pcf + ci_pcf (for approximated neutral current rms calculation) .
data sheet ade9078 rev. 0 | page 89 of 107 addr . name bits bit name settings description reset access 0x21d amtregion [31:4] reserved reserved. 0x0 r [3:0] aregion if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, these bits indicate which aigainx and aphcalx is currently being used . 0xf r 0000 aigain0, aphcal0. 0001 aigain1, aphcal1. 0010 aigain2, aphcal2. 0011 aigain3, aphcal3. 0100 aigain4, aphcal4. 1111 this feature is disabled because mten = 0 in the config0 register. 0x23d bmtregion [31:4] reserved reserved. 0x0 r [3:0] bregion if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, these bits indicate wh ich bigainx and bphcalx is currently being used . 0xf r 0000 bigain0, bphcal0. 0001 bigain1, bphcal1. 0010 bigain2, bphcal2. 0011 bigain3, bphcal3. 0100 bigain4, bphcal4. 1111 this feature is disabled because mten = 0 in the config0 register. 0x25d cmtregion [31:4] reserved reserved. 0x0 r [3:0] cregion if multipoint gain and phase compensation is enabled, with mten = 1 in the config0 register, these bits indicate which cigainx and cphcalx is currently being used . 0xf r 0000 cigain0, cphcal0. 0001 cigain1, cphcal1. 0010 cigain2, cphcal2. 0011 cigain3, cphcal3. 0100 cigain4, cphcal4. 1111 this feature is disabled because mten = 0 in the config0 register. 0x400 ipeak [31:27] reserved reserved. 0x0 r [26:24] ipphase these bits indicate which phases generate ipeakval value. note that the peaksel[2:0] bits in the config3 register determine which c urrent c hannel to monitor the peak value on. when ipphase , bit 0 is set to 1, phase a current generated ipeakval , bits [23:0] value. similarly, ipphase , bit 1 indicates phase b and ipphase , bit 2 indicates phase c current generated the peak value. 0x0 r [23:0] ipeakval the ipeak register stores the absolute value of the peak current. ipeak is equal to xi_pcf/2 5 . 0x0 r
ade9078 data sheet rev. 0 | page 90 of 107 addr . name bits bit name settings description reset access 0x401 vpeak [31:27] reserved reserved. 0x0 r [26:24] vpphase th ese bits indicate which phases generate vpeakval value. note that the peaksel[2:0] bits in the config3 register determine which voltage c hannels to monitor the peak value on. when vpphase[0] is 1, phase a voltage generated vpeakval[23:0] value. similarly, vpphase[1] indicates phase b a nd vpphase[2] indicates phase c voltage generated the peak value. 0x0 r [23:0] vpeakval the vpeak register stores the absolute value of the peak volt age. vpeak is equal to xv_pcf/2 5 . 0x0 r 0x402 status0 [31:25] reserved reserved. 0x0 r 24 mismtch this bit is set to indicate a change in the relationship between isumrms and isumlvl. 0x0 r/w1 23 coh_wfb_full this bit is set when the waveform buffer is full with resampled data, which is selected when wf_cap_sel = 0 in the wfb_cfg register. 0x0 r/w1 22 wfb_trig this bit is set when one of the events configured in wfb_trig_cfg occurs . 0x0 r/w1 21 pf_rdy this bit goes high to indicate when the power factor measurements have been updated, every 1.024 s ec. 0x0 r/w1 [20:19] reserved reserved. 0x0 r 18 pwrrdy this bit is set when the power values in the xwatt_acc, xva_acc, xvar_acc, xfvar_acc registers have been updated, after pwr_time 4 ksps samples . 0x0 r/w1 17 page_full this bit is set when a page enabled in the wfb_pg_irqen register has been filled with fixed data rate samples, when wf_cap_sel bit in the wfb_cfg register = 0 . 0x0 r/w1 16 wfb_trig_irq this bit is set when the waveform buffer has stopped filling after an event configured in wfb_trig_cfg occurs. this happens with fixed data rate samples only, when wf_cap_sel bit in the wfb_cfg register = 0 . 0x0 r/w1 15 dready this bit is set when new waveform samples are ready. the update rate depends on the data selected in the wf_src bits in the wfb_cfg register. 0x0 r/w1 14 cf4 this bit is set when a cf4 pulse is issued, when the cf4 pin goes from a high to low state . 0x0 r/w1 13 cf3 this bit is set when a cf3 pulse is issued, when the cf3 pin goes from a high to low state . 0x0 r/w1 12 cf2 this bit is set when a cf2 pulse is issued, when the cf2 pin goes from a high to low state . 0x0 r/w1 11 cf1 this bit is set when a cf1 pulse is issued, when the cf1 pin goes from a high to low state . 0x0 r/w1 10 revpsum4 this bit is set to indicate if the cf4 polarity changed sign. for example, if the last cf4 pulse was positive reactive energy and the next cf4 pulse is negative reactive energy, the revpsum4 bit is set. this bit is updated when a cf4 pulse is output, when the cf4 pin goes from high to low . 0x0 r/w1
data sheet ade9078 rev. 0 | page 91 of 107 addr . name bits bit name settings description reset access 9 revpsum3 this bit is set to indicate if the cf3 polarity changed sign. see revpsum4. 0x0 r/w1 8 revpsum2 this bit is set to indicate if the cf2 polarity changed sign. see revpsum4. 0x0 r/w1 7 revpsum1 this bit is set to indicate if the cf1 polarity changed sign. see revpsum4. 0x0 r/w1 6 revrpc this bit indicates if the phase c t otal or f undamental r eactive p ower has changed sign. the pwr_sign_sel bit in the ep_cfg register selects whether total or fundamental reactive power is monitored. this bit is updated when the power values in the xvar_acc and xfvar_acc registers have been updated, after pwr_time 4 ksps samp les . 0x0 r/w1 5 revrpb this bit indicates if the phase b total or fundamental reactive power has changed sign. see revrpc. 0x0 r/w1 4 revrpa this bit indicates if the phase a total or fundamental reactive power has changed sign. see revrpc. 0x0 r/w1 3 revapc this bit indicates if the phase c t otal a ctive p ower has changed sign . this bit is updated when the power values in the xwatt_acc and xwatt_acc registers have been updated, after pwr_time 4 ksps samples . 0x0 r/w1 2 revapb this bit indicates if the phase b t otal a ctive p ower has changed sign. see revapc. 0x0 r/w1 1 revapa this bit indicates if the phase a total active power has changed sign. see revapc. 0x0 r/w1 0 egyrdy this bit is set when the power values in the xwatthr, xvahr, xvarhr, xfvarhr registers have been updated, after egy_time 4 ksps samples or line cycles, depending on the egy_tmr_mode bit in the ep_cfg register . 0x0 r/w1 0x403 status1 31 error3 this bit indicates an error and generates a non - maskable interrupt. issue a software or hardware reset to clear this error. 0x0 r/w1 30 error2 this bit indicates that an error was detected and corrected. no action is required. 0x0 r/w1 29 error1 this bit indicates an error and generates a non - maskable interrupt. issue a software or hardware reset to clear this error. 0x0 r 28 error0 this bit indicates an error and generates a non - maskable interrupt. issue a software or hardware reset to clear this error. 0x0 r 27 crc_done this bit is set to indicate when the configuration register crc calculation is done, after initiated by writing the force_crc_update bit in the crc_force register . 0x0 r/w1 26 crc_chg this bit is set if any of the registers monitored by the configuration register crc change value. the crc_rslt register holds the new configuration register crc value. 0x0 r/w1 [25:19] reserved reserved. 0x0 r
ade9078 data sheet rev. 0 | page 92 of 107 addr . name bits bit name settings description reset access 18 seqerr this bit is set to indicate a phase sequence error on the phase voltage zero crossings . 0x0 r/w1 17 reserved reserved. 0x0 r 16 rstdone this bit is set to indicate that the ic has finished its power - up sequence after a reset or after changing between psm2 or psm3 operating mode to psm0 or psm1. this indicates that the user can configure the ic via the spi port. 0x0 r/w1 15 zxic when this bit is set to 1, it indicates a zero crossing has been detected on phase c current. 0x0 r/w1 14 zxib when this bit is set to 1, it indicates a zero crossing has been detected on phase b current. 0x0 r/w1 13 zxia when this bit is set to 1, it indicates a zero crossing has been detected on phase a current. 0x0 r/w1 12 zxcomb when this bit is set, it indicates a zero crossing has been detected on the combined signal from va, vb, and vc . 0x0 r/w1 11 zxvc when this bit is set, it indicates a zero crossing has been detected on the phase c voltage channel . 0x0 r/w1 10 zxvb when this bit is set, it indicates a zero crossing has been detected on the phase b voltage channel . 0x0 r/w1 9 zxva when this bit is set, it indicates a zero crossing has been detected on the phase a voltage channel . 0x0 r/w1 8 zxtovc this bit is set to indicate a z ero crossing timeout on phase c. this means that a zero crossing on the phase c voltage is missing. 0x0 r/w1 7 zxtovb this bit is set to indicate a zero crossing timeout on phase b. this means that a zero crossing on the phase b voltage is missing. 0x0 r/w1 6 zxtova this bit is set to indicate a zero crossing timeout on phase a. this means that a zero crossing on the phase a voltage is missing. 0x0 r/w1 5 reserved reserved. 0x0 r 4 rfnoload thi s bit is set when one or more phase fundamen tal reactive energy enters or exits the no load condition. the phase is indicated in the phnoload register. 0x0 r/w1 3 reserved reserved. 0x0 r 2 vanload this bit is set when one or more phase total apparent energy enters or exits the no load condition. the phase is indicated in the phnoload register. 0x0 r/w1 1 rnload this bit is set when one or more phase total reactive energy enters or exits the no load condition. the phase is indicated in the phnoload register. 0x0 r/w1 0 anload this bit is set when one or more phase total active energy enters or exits the no load condition. the phase is indicated in the phnoload register. 0x0 r/w1
data sheet ade9078 rev. 0 | page 93 of 107 addr . name bits bit name settings description reset access 0x404 event_status [31:17] reserved reserved. 0x0 r 16 dready this bit changes from a one to a zero when new waveform samples are ready. the update rate depends on the data selected in the wf_src bits in the wfb_cfg register. 0x0 r 15 reserved reserved. 0x0 r 14 rfnoload this bit is set when the f undamental r eactive e nergy accumulations in all phases are out of no load . this bit goes to zero when one or more phases of fundamental reactive energy accumulation goes into n o load . 0x0 r 13 reserved reserved. 0x0 r 12 vanload this bit is set when the t otal a pparent e nergy accumulations in all phases are out of no load . this bit goes to zero when one or more phases of total apparent energy accumulation goes into no load . 0x0 r 11 rnload this bit is set when the total reactive energy accumulations in all phases are out of no load . this bit goes to zero when one or more phases of total reactive energy accumulation goes into no load . 0x0 r 10 anload this bit is set when the total a ctive energy accumulations in all phases are out of no load . this bit goes to zero when one or more phases of total active energy accumulation goes into no load . 0x0 r 9 revpsum4 this bit indicates the sign of the last cf4 pulse. a zero indicates that the pulse was from negative energy and a one indicates that the energy was positive. this bit is updated when a cf4 pulse is output, when the cf4 pin goes from high to low . 0x0 r 8 revpsum3 this bit indicates the sign of the last cf3 pulse. a zero indicates that the pulse was from negative energy and a one indicates that the energy was positive. this bit is updated when a cf3 pulse is output, when the cf3 pin goes from high to low . 0x0 r 7 revpsum2 this bit indicates the sign of the last cf2 pulse. a zero indicates that the pulse was from negative energy and a one indicates that the energy was positive. this bit is updated when a cf2 pulse is output, when the cf2 pin goes from high to low . 0x0 r 6 revpsum1 this bit indicates the sign of the last cf1 pulse. a zero indicates that the pulse was from negative energy and a one indicates that the energy was positive. this bit is updated when a cf1 pulse is output, when the cf1 pin goes from high to low . 0x0 r [5:0] reserved reserved. 0x0 r 0x405 mask0 [31:25] reserved reserved. 0x0 r 24 mismtch set this bit to enable an interrupt when there is a change in the relationship between isumrms and isumlvl. 0x0 r/w 23 coh_wfb_full set this bit to enable an interrupt when the waveform buffer is full with resampled data, which is selected when wf_cap_sel = 0 in the wfb_cfg register. 0x0 r/w 22 wfb_trig set this bit to enable an interrupt when one of the events configured in wfb_trig_cfg occurs . 0x0 r/w
ade9078 data sheet rev. 0 | page 94 of 107 addr . name bits bit name settings description reset access 21 pf_rdy set this bit to enable an interrupt when the power factor measurements have been updated, every 1.024 s ec. 0x0 r/w [20:19] reserved reserved. 0x0 r 18 pwrrdy set this bit to enable an interrupt when the power values in the xwatt_acc, xva_acc, xvar_acc, xfvar_acc registers have been updated, after pwr_time 4 ksps samples . 0x0 r/w 17 page_full set this bit to enable an interrupt when a page enabled in the wfb_pg_irqen register has been filled. 0x0 r/w 16 wfb_trig_irq set this bit to enable an interrupt when this bit is set when the waveform buffer has stopped filling after an event configured in wfb_trig_cfg occurs . 0x0 r/w 15 dready set this bit to enable an interrupt when new waveform samples are ready. the update rate depends on the data selected in the wf_src bits in the wfb_cfg register. 0x0 r/w 14 cf4 set this bit to enable an interrupt when the cf4 pulse is issued, when the cf4 pin goes from a high to low state . 0x0 r/w 13 cf3 set this bit to enable an interrupt when the cf3 pulse is issued, when the cf3 pin goes from a high to low state . 0x0 r/w 12 cf2 set this bit to enable an interrupt when the cf2 pulse is issued, when the cf2 pin goes from a high to low state . 0x0 r/w 11 cf1 set this bit to enable an interrupt when the cf1 pulse is issued, when the cf1 pin goes from a high to low state . 0x0 r/w 10 revpsum4 set this bit to enable an interrupt when the cf4 polarity changed sign. 0x0 r/w 9 revpsum3 set this bit to enable an interrupt when the cf3 polarity changed sign. 0x0 r/w 8 revpsum2 set this bit to enable an interrupt when the cf2 polarity changed sign. 0x0 r/w 7 revpsum1 set this bit to enable an interrupt when the cf1 polarity changed sign. 0x0 r/w 6 revrpc set this bit to enable an interrupt when the phase c t otal or f undamental r eactive p ower has changed sign . 0x0 r/w 5 revrpb set this bit to enable an interrupt when the phase c t otal or f undamental r eactive p ower has changed sign . 0x0 r/w 4 revrpa set this bit to enable an interrupt when the phase a total or fundamental reactive power has changed sign . 0x0 r/w 3 revapc s et this bit to enable an interrupt when the phase c t otal a ctive p ower has changed sign. 0x0 r/w 2 revapb set this bit to enable an interrupt when the phase b total active power has changed sign. 0x0 r/w
data sheet ade9078 rev. 0 | page 95 of 107 addr . name bits bit name settings description reset access 1 revapa set this bit to enable an interrupt when the phase a total active power has changed sign. 0x0 r/w 0 egyrdy set this bit to enable an interrupt when the power values in the xwatthr, xvahr, xvarhr, and xfvarhr registers have been updated, after egy_time 4 ksps samples or line cycles, depending on the egy_tmr_mode bit in the ep_cfg register . 0x0 r/w 0x406 mask1 31 error3 set this bit to enable an interrupt if error3 occurs. issue a software reset or hardware reset to clear this error. 0x0 r/w 30 error2 set thi s bit to enable an interrupt if error2 occurs . 0x0 r/w 29 error1 this interrupt is not maskable. issue a software reset or hardware reset to clear this error. 0x0 r/w 28 error0 this interrupt is not maskable. issue a software reset or hardware reset to clear this error. 0x0 r/w 27 crc_done set this bit to enable an interrupt when the configuration register crc calculation is done, after initiated by writing the force_crc_update bit in the crc_force register . 0x0 r/w 26 crc_chg set this bit to enable an interrupt if any of the registers monitored by the configuration register crc change value. the crc_rslt register holds the new configuration register crc value. 0x0 r/w [25:19] reserved reserved. 0x0 r 18 seqerr set this bit to set an interrupt when on a phase sequence error on the p hase v oltage zero crossings . 0x0 r/w [17:16] reserved reserved. 0x0 r 15 zxic set this bit to set an interrupt when a zero crossing has been detected on the phase c current channel . 0x0 r/w 14 zxib set this bit to set an interrupt when a zero crossing has been detected on the phase b current channel . 0x0 r/w 13 zxia set this bit to set an interrupt when a zero crossing has been detected on the phase a current channel . 0x0 r/w 12 zxcomb set this bit to set an interrupt when a zero crossing has been detected on the combined signal from va, vb, and vc . 0x0 r/w 11 zxvc set this bit to set an interrupt when a zero crossing has been detected on the phase c voltage channel . 0x0 r/w 10 zxvb set this bit to set an interrupt when a zero crossing has been detected on the phase b voltage channel . 0x0 r/w 9 zxva set this bit to set an interrupt when a zero crossing h as been detected on the phase a voltage channel . 0x0 r/w 8 zxtovc set this bit to set an interrupt when there is a z ero crossing timeout on phase c. this means that a zero crossing on the phase c voltage is missing. 0x0 r/w 7 zxtovb set this bit to set an interrupt when there is a zero crossing timeout on phase b. this means that a zero crossing on the phase b voltage is missing. 0x0 r/w
ade9078 data sheet rev. 0 | page 96 of 107 addr . name bits bit name settings description reset access 6 zxtova set this bit to set an interrupt when there is a zero crossing timeout on phase a. this means that a zero crossing on the phase a voltage is missing. 0x0 r/w 5 reserved reserved. 0x0 r 4 rfnoload set this bit to set an interrupt when one or more phase total reactive energy enters or exits the no load condition . 0x0 r/w 3 reserved reserved. 0x0 r 2 vanload set this bit to set an interrupt when one or more phase total apparent energy enters or exits the no load condition . 0x0 r/w 1 rnload set this bit to set an interrupt when one or more phase total reactive energy enters or exits the no load condition . 0x0 r/w 0 anload set this bit to set an interrupt when one or more phase total active energy enters or exits the no load condition . 0x0 r/w 0x407 event_mask [31:17] reserved reserved. 0x0 r 16 dready set this bit to enable the event pin to go low when new waveform samples are ready. the update rate depends on the data selected in the wf_src bits in the wfb_cfg register . 0x0 r/w 15 reserved reserved. 0x0 r 14 rfnoload set this bit to enable the event pin to go low when one or more phases of f undamental r eactive energy accumulation goes into n o load . 0x0 r/w 13 reserved reserved. 0x0 r 12 vanload set this bit to enable the event pin to go low when one or more phases of t otal a pparent energy accumulation goes into no load . 0x0 r/w 11 rnload set this bit to enable the event pin to go low when one or more phases of t otal r eactive energy accumulation goes into no load . 0x0 r/w 10 anload set this bit to enable the event pin to go low when one or more phases of t otal a ctive energy accumulation goes into no load . 0x0 r/w 9 revpsum4 set this bit to enable the event pin to go low to indicate if the last cf4 pulse was from negative energy. this bit is updated when a cf4 pulse is output, when the cf4 pin goes from high to low . 0x0 r/w 8 revpsum3 set this bit to enable the event pin to go low to indicate if the last cf3 pulse was from negative energy. this bit is updated when a cf3 pulse is output, when the cf3 pin goes from high to low . 0x0 r/w 7 revpsum2 set this bit to enable the event pin to go low to indicate if the last cf2 pulse was from negative energy. this bit is updated when a cf2 pulse is output, when the cf2 pin goes from high to low . 0x0 r/w 6 revpsum1 set this bit to enable the event pin to go low to indicate if the last cf1 pulse was from negative energy. this bit is updated when a cf1 pulse is output, when the cf1 pin goes from high to low . 0x0 r/w [5:0] reserved reserved. 0x0 r
data sheet ade9078 rev. 0 | page 97 of 107 addr . name bits bit name settings description reset access 0x40f vlevel [31:24] reserved reserved. 0x0 r [23:0] vlevel_val register used in the algorithm that computes the fundamental reactive powe r. 0x45d45 r/w 0x41f phnoload [31:17] reserved reserved. 0x0 r 16 cfvarnl this bit is set if the phase c fundamental r eactive e nergy is in n o l oad . 0x0 r 15 reserved reserved. 0x0 r 14 cvanl this bit is set if the phase c t otal a pparent e nergy is in no load . 0x0 r 13 cvarnl this bit is set if the phase b t otal r eactive e nergy is in no load . 0x0 r 12 cwat tnl this bit is set if the phase c t otal a ctive e nergy is in no load . 0x0 r 11 reserved reserved. 0x0 r 10 bfvarnl this bit is set if the phase b fundamental reactive energy is in no load. 0x0 r 9 reserved reserved. 0x0 r 8 bvanl this bit is set if the phase b total apparent energy is in no load . 0x0 r 7 bvarnl this bit is set if the phase b total reactive energy is in no load. 0x0 r 6 bwat tnl this bit is set if the phase b total active energy is in no load. 0x0 r 5 reserved reserved. 0x0 r 4 afvarnl this bit is set if the phase a fundamental reactive energy is in no load. 0x0 r 3 reserved reserved. 0x0 r 2 avanl this bit is set if the phase a total apparent energy is in no load . 0x0 r 1 avarnl this bit is set if the phase a total reactive energy is in no load. 0x0 r 0 awat tnl this bit is set if the phase a total active energy is in no load. 0x0 r 0x424 adc_redirect [31:21] reserved reserved. 0x0 r [20:18] vc_din voltage c c hannel d ata can be selected from: 0x7 r/w 000 ia adc data. 001 ib adc data. 010 ic adc data. 011 in adc d ata. 100 va adc d ata. 101 vb adc d ata. 110 vc adc data. 111 vc adc data. [17:15] vb_din vb channel data can be selected from all channels. the bit descriptions for 000b through 110b match vc_din. when the value is equal to 111b then: 0x7 r/w 111 vb adc data.
ade9078 data sheet rev. 0 | page 98 of 107 addr . name bits bit name settings description reset access [14:12] va_din va channel data can be selected from all channels. the bit descriptions for 000b through 110b match vc_din. when the value is equal to 111b then: 0x7 r/w 111 va adc data. [11:9] in_din in channel data can be selected from all channels. the bit descriptions for 000b through 110b match vc_din. when the value is equal to 111b then: 0x7 r/w 111 in adc data. [8:6] ic_din ic channel data can be selected from all channels. the bit descriptions for 000b through 110b match vc_din. when the value is equal to 111b then: 0x7 r/w 111 ic adc data. [5:3] ib_din ib channel data can be selected from all channels. the bit descriptions for 000b through 110b match vc_din. when the value is equal to 111b then: 0x7 r/w 111 ib adc data. [2:0] ia_din ia channel data can be selected from all channels. the bit descriptions for 000b through 110b match vc_din. when the value is equal to 111b then: 0x7 r/w 111 ia adc data. 0x425 cf_lcfg [31:23] reserved reserved. 0x0 r 22 cf4_lt if this bit is set, the cf4 pulse width is determined by the cf_ltmr register value. if this bit = 0, the active low pulse width is set at 80 ms for frequencies lower than 6.25 hz. 0x0 r/w 21 cf3_lt if this bit is set, the cf3 pulse width is determined by the cf_ltmr register value. if this bit = 0, the active low pulse width is set at 80 ms for frequencies lower than 6.25 hz. 0x0 r/w 20 cf2_lt if this bit is set, the cf2 pulse width is determined by the cf_ltmr register value. if this bit = 0, the active low pulse width is set at 80 ms for frequencies lower than 6.25 hz. 0x0 r/w 19 cf1_lt if this bit is set, the cf1 pulse width is determined by the cf_ltmr register value. if this bit = 0 , the active low pulse width is set at 80 ms for frequencies lower than 6.25 hz. 0x0 r/w [18:0] cf_ltmr if the cfx_lt bit in cf_lcfg register is set, this value determines the active low pulse width of the cfx pulse . 0x0 r/w 0x472 part_id [31:22] reserved reserved. 0x0 r 21 ad73370_id this bit is set to identify an ad73370 ic . 0x0 r 20 ade9000_id this bit is set to identify an ade9000 ic . 0x0 r [19:17] reserved reserved. 0x0 r 16 ade9004_id this bit is set to identify an ade9004 ic . 0x0 r [15:0] reserved reserved. 0x0 r
data sheet ade9078 rev. 0 | page 99 of 107 addr . name bits bit name settings description reset access 0x481 config1 15 ext_ref set this bit if using an external voltage reference. 0x0 r/w [14:13] reserved reserved. 0x0 r 12 irq0_on_irq1 set this bit to combine all the interrupts onto a single interrupt pin, irq1, instead of using two pins, irq0 and irq1. note that the irq0 pin still indicate s the enabled irq0 events while in this mode and the irq1 indicates both irq1 and irq0 events. 0x0 r/w 11 burst_en set this bit to enable burst read functionality on the registers from address 0x500 to address 0x 6ff. note that this bit disables the crc being appended to spi r egister r eads . 0x0 r/w 10 reserved reserved. 0x0 r [9:8] pwr_settle these bits configure the time for the power and filter based rms measurements to settle before starting the power, energy and cf accumulations. 0x0 r/w 0: 64 ms. 1: 128 ms. 2: 256 ms. 3: 0 ms. [7:6] reserved reserved. 0x0 r 5 cf_acc_clr set this bit to clear the accumulation in the digital to frequency converter and cfden counter. note that this bit automatically clears itself. 0x0 w 4 reserved reserved. 0x0 r [3:2] cf4_cfg these bits select which function to output on the cf4 pin . 0x0 r/w 00 cf4, from digital to frequency converter. 01 cf4, from digital to frequency converter. 10 event. 11 dready. 1 cf3_cfg this bit selects which function to output on the cf3 pin . 0x0 r/w 0 cf3, from digital to frequency converter. 1 zero crossing output selected by the zx_sel bits in the zx_lp_sel register. 0 swrst set this bit to initiate a software reset. note that this bit is self clearing. 0x0 w1 0x490 cfmode 15 cf4dis cf4 output disable. set this bit to disable the cf4 output and bring the pin high. note that when this bit is set, the cfx bit in status0 is not set when a cf pulse is accumulated in the digital to frequency converter. 0x0 r/w 14 cf3dis cf3 output disable -- see cf4dis. 0x0 r/w 13 cf2dis cf2 output disable -- see cf4dis. 0x0 r/w 12 cf1dis cf1 output disable -- see cf4dis 0x0 r/w
ade9078 data sheet rev. 0 | page 100 of 107 addr . name bits bit name settings description reset access [11:9] cf4sel type of energy output on the cf4 pin. configure termsel4 in the compmode register to select which phases are included. 0x0 r/w 000 total a ctive p ower. 001 total r eactive p ower. 010 total a pparent p ower. 100 fundamental r eactive power . 110 total active power . 111 total active power . [8:6] cf3sel selects type of energy output on cf3 pin -- see cf4sel . 0x0 r/w [5:3] cf2sel selects type of energy output on cf2 pin -- see cf4sel. 0x0 r/w [2:0] cf1sel selects type of energy output on cf1 pin -- see cf4sel. 0x0 r/w 0x491 compmode [15:12] reserved reserved. 0x0 r [11:9] termsel4 phases to include in cf4 pulse output. set the termsel4[2] bit to one to include phase c in the cf4 pulse output. similarly, set termsel4[1] to include phase b and termsel4[0] for phase a. 0x0 r/w [8:6] termsel3 phases to include in cf3 pulse output -- see termsel4. 0x0 r/w [5:3] termsel2 phases to include in cf2 pulse output -- see termsel4. 0x0 r/w [2:0] termsel1 phases to include in cf1 pulse output -- see termsel4. 0x0 r/w 0x492 accmode [15:9] reserved reserved. 0x0 r 8 selfreq this bit is used to configure the ic for a 50 hz or 60 hz system. this setting is used in the fundamental reactive power measurement and to set the default line period used for resampling calculations if a zero crossing is not present. 0x0 r/w 0 50 hz. 1 60 hz. 7 iconsel set this bit to calculate the current flowing through ib from the ia and ic measurements. if this bit is set, ib = ? ia ? ic . 0x0 r/w [6:4] vconsel three - wire and f our - wire hardware configuration selection . 0x0 r/w 000 4 - wire w ye. 001 3 - wire d elta. vb' = va ? vc. 010 4 - wire wye , n on -bl ondel c ompliant. vb' = ? va ? vc. 011 4 - wire delta , non - blondel compliant . vb' = ? va. 100 3 - wire delta . va' = va ? vb; vb' = va ? vc; vc' = vc ? vb.
data sheet ade9078 rev. 0 | page 101 of 107 addr . name bits bit name settings description reset access [3:2] varacc total and f undamental reactive power accumulation mode for e nergy registers and cfx pulses . 0x0 r/w 00 signed a ccumu l ation m ode. 01 absolute value accumulation mode . 10 positive accumulation mode . 11 negative accumulation mode . [1:0] wat tacc total and fundamental active power accumulation mode for energy registers and cfx pulses -- see varacc. 0x0 r/w 0x493 config3 [15:5] reserved reserved. 0x0 r [4:2] peaksel set this bit to select which phase(s) to monitor peak voltages and currents on. write peaksel[0] to one to enable phase a peak detection. similarly, peaksel[1] enables phase b peak detection and peaksel[2] enables phase c peak detection. 0x0 r/w [1:0] reserved reserved. 0x0 r 0x49a zx_lp_sel [15:5] reserved reserved. 0x0 r [4:3] lp_sel selects line period measurement used for resampling. 0x3 r/w 00 aperiod, line period measurement from phase a v oltage. 01 bperiod, line period measurement from phase b voltage . 10 cperiod, line period measurement from phase c voltage . 11 com_period, line period measurement on combined signal from va, vb, and vc. [2:1] zx_sel selects the zero - crossing signal , which can be routed to cf3/zx output pin and which is used for line cycle energy accumulation . 0x3 r/w 00 zxva, phase a v oltage z ero - crossing signal. 01 zxvb, phase b voltage zero - crossing signal. 10 zxvc, phase c voltage zero - crossing signal. 11 zxcomb, zero crossing on combined signal from va, vb, and vc. 0 reserved reserved. 0x0 r 0x49d phsign [15:10] reserved reserved. 0x0 r 9 sum4sign sign of the sum of the powers included in the cf4 datapath. the cf4 energy is positive if this bit is clear and negative if this bit is set. 0x0 r 8 sum3sign sign of the sum of the powers included in the cf3 datapath. the cf3 energy is positive if this bit is clear and negative if this bit is set. 0x0 r 7 sum2sign sign of the sum of the powers included in the cf2 datapath. the cf2 energy is positive if this bit is clear and negative if this bit is set. 0x0 r 6 sum1sign sign of the sum of the powers included in the cf1 datapath. the cf1 energy is positive if this bit is clear and negative if this bit is set. 0x0 r
ade9078 data sheet rev. 0 | page 102 of 107 addr . name bits bit name settings description reset access 5 cvarsign phase c r eactive p ower s ign bit. the pwr_sign_sel bit in the ep_cfg selects whether this feature monitors total or fundamental reactive power. 0x0 r 4 cwsign phase c a ctive p ower s ign bit. 0x0 r 3 bvarsign phase b reactive power sign bit. the pwr_sign_sel bit in the ep_cfg selects whether this feature monitors total or fundamental reactive power. 0x0 r 2 bwsign phase b active power sign bit. 0x0 r 1 avarsign phase a reactive power sign bit. the pwr_sign_sel bit in the ep_cfg selects whether this feature monitors total or fundamental reactive power. 0x0 r 0 awsign phase a active power sign bit. 0x0 r 0x4a0 wfb_cfg [15:13] reserved reserved. 0x0 r 12 wf_in_en this setting determines whether the in waveform samples are read out of the waveform buffer through spi . 0x0 r/w 0 in waveform samples are not read out of w aveform b uffer through spi. 1 in waveform samples are read out of waveform buffer through spi. [11:10] reserved reserved. 0x0 r [9:8] wf_src waveform b uffer s ource and dready, d ata r eady u pdate r ate, s election . 0x0 r/w 00 s inc4 output, at 16 ksps . 01 reserved. 10 s inc4 + iir lpf output, at 4 ksps . 11 current and v oltage c hannel w aveform samples, processed by the dsp (xi_pcf, xv_pcf) at 4 ksps . [7:6] wf_mode fixed d ata r ate w aveforms f illing and t rigger b ased m odes . 0x0 r/w 00 stop when w aveform b uffer is f ull. 01 continuous f ill s top only on e nabled t rigger e vents. 10 continuous f illing c enter c apture around enabled trigger events . 11 continuous fill s ave e vent a ddress of enabled trigger events . 5 wf_cap_sel this bit selects whether the w aveform b uffer is filled with r esampled d ata or f ixed d ata r ate d ata, selected in the wf_cap_sel bits . 0x0 r/w 0 resampled data . 1 fixed data rate data .
data sheet ade9078 rev. 0 | page 103 of 107 addr . name bits bit name settings description reset access 4 wf_cap_en when this bit is set, a waveform capture is started . 0x0 r/w 0 the waveform capture is disabled. the w aveform b uffer contents are maintained. 1 the waveform capture is started, according to the type of capture in wf_cap_sel and the wf_src bits when this bit goes from a 0 to a 1. [3:0] burst_chan selects which data to read out of the waveform buffer through spi . 0x0 r/w 0000 all channels. 0001 ia and va. 0010 ib and vb. 0011 ic and vc. 1000 ia. 1001 va. 1010 ib. 1011 vb. 1100 ic. 1101 vc. 1110 in if wf_in_en = 1 in the wfb_cfg register. 1111 single a ddress r ead (spi b urst r ead m ode is disabled) . 0x4a2 wfb_trg_cfg [15:11] reserved reserved. 0x0 r 10 trig_force set this bit to trigger an event to stop the waveform buffer filling . 0x0 r/w 9 zxcomb zero crossing on combined signal from va, vb, and vc . 0x0 r/w zxvc phase c voltage zero crossing. 0x0 r/w 7 zxvb phase b voltage zero crossing. 0x0 r/w 6 zxva phase a voltage zero crossing. 0x0 r/w 5 zxic phase c current zero crossing. 0x0 r/w 4 zxib phase b current zero crossing. 0x0 r/w 3 zxia phase a current zero crossing. 0x0 r/w [2:0] reserved reserved. 0x0 r 0x4a3 wfb_trg_stat [15:12] wfb_last_page these bits indicate which page of the waveform buffer was filled last, when filling with fixed rate data samples. 0x0 r/w 11 reserved reserved. 0x0 r [10:0] wfb_trig_addr this holds the address of the last sample put into the waveform buffer after a trigger event occurred, which is within a sample or two of when the actual trigger event occurred. 0x0 r 0x4af config2 [15:13] reserved reserved. 0x0 r 12 uperiod_sel set this bit to use a user configured line period, in user_period, for the resampling calculation. if this bit is clear, the phase voltage line period selected by the lp_sel[1:0] bits in the zx_lp_sel register is used. 0x0 r/w
ade9078 data sheet rev. 0 | page 104 of 107 addr . name bits bit name settings description reset access [11:9] hpf_crn high - pass filter corner (f3db) enabled when the hpfdis bit in the config0 register = 0 . 0x6 r/w 000 38.695 hz. 001 19.6375 hz. 010 9.895 hz. 011 4.9675 hz. 100 2.49 hz. 101 1.2475 hz. 110 0.625 hz. 111 0.3125 hz. [8:0] reserved reserved. 0x0 r 0x4b0 ep_cfg [15:13] noload_tmr this register configures how many 4 ksps samples to evaluate the no load condition over. 0x0 r/w 000 64. 001 128. 010 256. 011 512. 100 1024. 101 2048. 110 4096. 111 disable no load threshold. [12:8] reserved reserved. 0x0 r 7 pwr_sign_sel selects whether the revrpx bit follows the sign of the total or fundamental reactive power. 0x0 r/w 0 total reactive power. 1 fundamental reactive power. 6 reserved reserved. 0x0 r 5 rd_rst_en set this bit to enable the energy register read with reset feature. if this bit is set, when one of the xwatthr, xvahr, xvarhr and xfvarhr register is read, it is reset and begins accumulating energy from zero. 0x0 r/w 4 egy_ld_accum if this bit = 0 , the internal energy register is added to the user accessible energy register. if the bit is set, the internal energy register overwrites the user accessible energy register when the egyrdy event occurs. 0x0 r/w [3:2] reserved reserved. 0x0 r 1 egy_tmr_mode this bit determines whether energy is accumulated based on the number of 4 ksps samples or zero crossing events configured in the egy_time register. 0x0 r/w 0 accumulate energy based on 4 ksps samples. 1 accumulate energy based on the zero crossing selected by the zx_sel bits in the zx_lp_sel register. 0 egy_pwr_en set this bit to enable the energy and power accumulator, when the run bit is also set. 0x0 r/w
data sheet ade9078 rev. 0 | page 105 of 107 addr . name bits bit name settings description reset access 0x4b4 crc_force [15:1] reserved reserved. 0x0 r 0 force_crc_update write this bit to force the configuration register crc calculation to start. when the calculation is complete, the crc_done bit is set in the status1 register. 0x0 r/w 0x4b5 crc_opten 15 crc_wfb_trg_cfg_en set this bit to include the wfb_trg_cfg register in the configuration register crc calculation. 0x0 r/w 14 crc_wfb_pg_irqen set this bit to include the wfb_pg_irqen register in the configuration register crc calculation. 0x0 r/w 13 crc_wfb_cfg_en set this bit to include the wfb_cfg register in the configuration register crc calculation. 0x0 r/w 12 crc_seq_cyc_en set this bit to include the seq_cyc register in the configuration register crc calculation. 0x0 r/w 11 crc_zxlpsel_en set this bit to include the zx_lp_sel register in the configuration register crc calculation. 0x0 r/w 10 crc_zxtout_en set this bit to include the crc_zxtout_en register in the configuration register crc calculation. 0x0 r/w 9 crc_app_nl_lvl_en set this bit to include the app_nl_lvl register in the configuration register crc calculation. 0x0 r/w 8 crc_react_nl_lvl_en set this bit to include the react_nl_lvl register in the configuration register crc calculation. 0x0 r/w 7 crc_act_nl_lvl_en set this bit to include the act_nl_lvl register in the configuration register crc calculation. 0x0 r/w [6:3] reserved reserved. 0x0 r 2 crc_event_mask_en set this bit to include the event_mask register in the configuration register crc calculation. 0x0 r/w 1 crc_mask1_en set this bit to include the mask1 register in the configuration register crc calculation. 0x0 r/w 0 crc_mask0_en set this bit to include the mask0 register in the configuration register crc calculation. 0x0 r/w 0x4b8 psm2_cfg [15:9] reserved reserved. 0x0 r [8:5] pkdet_lvl these bits configure the psm2 low power comparator peak current detection level, listed as the input signal level with respect to full scale. the register value is retained in psm2 and psm3. it returns to its default value if psm0 is entered. 0x0 r/w 0000 100:1. 0001 200:1. 0010 300:1. 0011 400:1. 0100 500:1. 0101 600:1. 0110 700:1. 0111 800:1. 1000 900:1. 1001 1000:1. 1010 1100:1. 1011 1200:1.
ade9078 data sheet rev. 0 | page 106 of 107 addr . name bits bit name settings description reset access 1100 1300:1. 1101 1400:1. 1110 1500:1. 1111 1600:1. [4:0] lpline this register determines the time used to detect peak currents in the low power comparator in psm2 operating mode. note that this register retains its value in psm2 and psm3 operating modes but is reset to its default value upon entering psm0 or psm 1. 0x1f r/w 0x4b9 pga_gain [15:14] reserved reserved. 0x0 r [13:12] vc_gain pga gain for voltage channel c adc. 0x0 r/w 00 gain = 1. 01 gain = 2. 10 gain = 4. 11 gain = 4. [11:10] vb_gain pga gain for voltage channel b adc. see vc_gain. 0x0 r/w [9:8] va_gain pga gain for voltage channel a adc. see vc_gain. 0x0 r/w [7:6] in_gain pga gain for neutral current channel adc. see vc_gain. 0x0 r/w [5:4] ic_gain pga gain for current channel c adc. see vc_gain. 0x0 r/w [3:2] ib_gain pga gain for voltage channel b adc. see vc_gain. 0x0 r/w [1:0] ia_gain pga gain for current channel a adc. see vc_gain. 0x0 r/w 0x4ba chnl_dis [15:7] reserved reserved. 0x0 r 6 vc_disadc set this bit to one to disable the adc. 0x0 r/w 5 vb_disadc set this bit to one to disable the adc. 0x0 r/w 4 va_disadc set this bit to one to disable the adc. 0x0 r/w 3 in_disadc set this bit to one to disable the adc. 0x0 r/w 2 ic_disadc set this bit to one to disable the adc. 0x0 r/w 1 ib_disadc set this bit to one to disable the adc. 0x0 r/w 0 ia_disadc set this bit to one to disable the adc. 0x0 r/w 0x4e0 var_dis [15:1] reserved reserved. 0x0 r 0 vardis set this bit to disable the total var calculation. this bit must be set before writing the run bit for proper operation. 0x0 r/w
data sheet ade9078 rev. 0| page 107 of 107 outline dimensions 03-08-2016-a 0.50 bsc bottom view top view pin 1 indicator p i n 1 i n d i c a t o r seating plane 0.05 max 0.02 nom 0.203 ref coplanarity 0.08 0.30 0.25 0.18 6.10 6.00 sq 5.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.45 0.40 0.35 0.20 min 4.70 4.60 sq 4.50 compliant to jedec standards mo-220-wjjd-5 40 1 11 10 20 21 30 31 end view exposed pad pkg-005131 figure 114. 40-lead lead frame chip scale package [lfcsp] 6 mm 6 mm body and 0.75 mm package height (cp-40-7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ade9078acpz ?40c to +85c 40-lead lead frame chip scale package [lfcsp] cp-40-7 ade9078acpz-rl ?40c to +85c 40-lead lead frame chip scale package [lfcsp], 13 tape and reel cp-40-7 EVAL-ADE9078EBZ evaluation board 1 z = rohs compliant part. ?2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d14331-0-8/16(0)

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